ST7FDALI View Datasheet(PDF) - STMicroelectronics

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Description

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ST7FDALI

8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI, DALI

STMicroelectronics 

I/O PORTS (Cont’d)

Figure 30. I/O Port General Block Diagram

REGISTER

ACCESS

DR

ALTERNATE

OUTPUT

1

From on-chip peripheral

0

ALTERNATE

ENABLE

BIT

ST7DALI

VDD

P-BUFFER

(see table below)

PULL-UP

(see table below)

VDD

DDR

OR

OR SEL

If implemented

DDR SEL

DR SEL

1

0

PULL-UP

CONDITION

N-BUFFER

CMOS

SCHMITT

TRIGGER

EXTERNAL

INTERRUPT

Combinational

Logic

REQUEST (eix)

SENSITIVITY

SELECTION

FROM

OTHER

BITS Note: Refer to the Port Configuration

table for device specific information.

PAD

DIODES

(see table below)

ANALOG

INPUT

ALTERNATE

INPUT

To on-chip peripheral

Table 8. I/O Port Mode Options

Configuration Mode

Input

Output

Floating with/without Interrupt

Pull-up with/without Interrupt

Push-pull

Open Drain (logic level)

True Open Drain

Legend: NI - not implemented

Off - implemented not activated

On - implemented and activated

Pull-Up

Off

On

Off

NI

P-Buffer

Off

On

Off

NI

Diodes

to VDD

to VSS

On

On

NI (see note)

Note: The diode to VDD is not implemented in the

true open drain pads. A local protection between

the pad and VOL is implemented to protect the de-

vice against positive stress.

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