ST7FDALI View Datasheet(PDF) - STMicroelectronics

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ST7FDALI

8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI, DALI

STMicroelectronics 

ST7DALI

RESET SEQUENCE MANAGER (Cont’d)

The RESET pin is an asynchronous signal which

plays a major role in EMS performance. In a noisy

environment, it is recommended to follow the

guidelines mentioned in the electrical characteris-

tics section.

7.5.3 External Power-On RESET

If the LVD is disabled by option byte, to start up the

microcontroller correctly, the user must ensure by

means of an external reset circuit that the reset

signal is held low until VDD is over the minimum

level specified for the selected fOSC frequency.

A proper reset signal for a slow rising VDD supply

can generally be provided by an external RC net-

work connected to the RESET pin.

Figure 15. RESET Sequences

VDD

VIT+(LVD)

VIT-(LVD)

7.5.4 Internal Low Voltage Detector (LVD)

RESET

Two different RESET sequences caused by the in-

ternal LVD circuitry can be distinguished:

■ Power-On RESET

■ Voltage Drop RESET

The device RESET pin acts as an output that is

pulled low when VDD<VIT+ (rising edge) or

VDD<VIT- (falling edge) as shown in Figure 15.

The LVD filters spikes on VDD larger than tg(VDD) to

avoid parasitic resets.

7.5.5 Internal Watchdog RESET

The RESET sequence generated by a internal

Watchdog counter overflow is shown in Figure 15.

Starting from the Watchdog counter underflow, the

device RESET pin acts as an output that is pulled

low during at least tw(RSTL)out.

RUN

LVD

RESET

ACTIVE PHASE

RUN

EXTERNAL

RESET

ACTIVE

PHASE

RUN

WATCHDOG

RESET

ACTIVE

PHASE

RUN

EXTERNAL

RESET

SOURCE

RESET PIN

WATCHDOG

RESET

th(RSTL)in

tw(RSTL)out

WATCHDOG UNDERFLOW

INTERNAL RESET (256 or 4096 TCPU)

VECTOR FETCH

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