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ADC08100 View Datasheet(PDF) - National ->Texas Instruments

Part NameDescriptionManufacturer
ADC08100 8-Bit, 20 Msps to 100 Msps, 1.3 mW/Msps A/D Converter National-Semiconductor
National ->Texas Instruments National-Semiconductor
ADC08100 Datasheet PDF : 20 Pages
First Prev 11 12 13 14 15 16 17 18 19 20
FIGURE 6. Isolating the ADC Clock from Digital Circuitry
Driving the inputs (analog or digital) beyond the power
supply rails. For proper operation, all inputs should not go
more than 300 mV below the ground pins or 300 mV above
the supply pins. Exceeding these limits on even a transient
basis may cause faulty or erratic operation. It is not uncom-
mon for high speed digital circuits (e.g., 74F and 74AC de-
vices) to exhibit undershoot that goes more than a volt below
ground. A 51resistor in series with the offending digital input
will usually eliminate the problem.
Care should be taken not to overdrive the inputs of the
ADC08100. Such practice may lead to conversion inaccura-
cies and even to device damage.
Attempting to drive a high capacitance digital data bus.
The more capacitance the output drivers must charge for
each conversion, the more instantaneous digital current is re-
quired from DR VD and DR GND. These large charging cur-
rent spikes can couple into the analog section, degrading
dynamic performance. Buffering the digital data outputs (with
a 74F541, for example) may be necessary if the data bus ca-
pacitance exceeds 10 pF. Dynamic performance can also be
improved by adding 100series resistors at each digital out-
put, reducing the energy coupled back into the converter input
Using an inadequate amplifier to drive the analog input.
As explained in Section 2.0, the capacitance seen at the input
alternates between 3 pF and 4 pF with the clock. This dynamic
capacitance is more difficult to drive than is a fixed capaci-
tance, and should be considered when choosing a driving
device. The LMH6702 and the LMH6628 have been found to
be good devices for driving the ADC08100.
Driving the VRT pin or the VRB pin with devices that can
not source or sink the current required by the ladder. As
mentioned in Section 1.0, care should be taken to see that
any driving devices can source sufficient current into the
VRT pin and sink sufficient current from the VRB pin. If these
pins are not driven with devices than can handle the required
current, these reference pins will not be stable, resulting in a
reduction of dynamic performance.
Using a clock source with excessive jitter, using an ex-
cessively long clock signal trace, or having other signals
coupled to the clock signal trace. This will cause the sam-
pling interval to vary, causing excessive output noise and a
reduction in SNR performance. The use of simple gates with
RC timing is generally inadequate as a clock source.
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