|ADC08100||8-Bit, 20 Msps to 100 Msps, 1.3 mW/Msps A/D Converter|
National ->Texas Instruments
|ADC08100 Datasheet PDF : 20 Pages |
4.2 The ADC08100 Clock
Although the ADC08100 is tested and its performance is
guaranteed with a 100 MHz clock, it typically will function well
with clock frequencies from 20 MHz to 125 MHz.
Halting the clock will provide nearly as much power saving as
raising the PD pin high. Typical power consumption with a
stopped clock is 3 mW, compared to 1 mW when PD is high.
The digital outputs will remain in the same state as they were
before the clock was halted.
Once the clock is restored (or the PD pin is brought low), there
is a time of about 1 microsecond before the output data is
valid. However, because of the linear relationship between
total power consumption and clock frequency, the part re-
quires about one microsecond after the clock is restarted or
substantially changed in frequency before the part returns to
its specified accuracy.
The low and high times of the clock signal can affect the per-
formance of any A/D Converter. Because achieving a precise
duty cycle is difficult, the ADC08100 is designed to maintain
performance over a range of duty cycles. While it is specified
and performance is guaranteed with a 50% clock duty cycle
and 100 Msps, ADC08100 performance is typically main-
tained with clock high and low times of 2 ns, corresponding to
a clock duty cycle range of 20% to 80% with a 100 MHz clock.
Note that the clock high and low times of 2 ns may not be
The CLOCK line should be series terminated at the clock
source in the characteristic impedance of that line. If the clock
line is longer than
analog circuitry can lead to poor performance that may seem
impossible to isolate and remedy. The solution is to keep the
analog circuitry well separated from the digital circuitry.
High power digital components should not be located on or
near a straight line between the ADC or any linear component
and the power supply area as the resulting common return
current path could cause fluctuation in the analog input
“ground” return of the ADC.
The DR Gnd connection to the ground plane should not use
the same feedthrough use by other ground connections.
Generally, analog and digital lines should cross each other at
90° to avoid getting digital noise into the analog path. In high
frequency systems, however, avoid crossing analog and dig-
ital lines altogether. Clock lines should be isolated from ALL
other lines, analog AND digital. Even the generally accepted
90° crossing should be avoided as even a little coupling can
cause problems at high frequencies. Best performance at
high frequencies is obtained with a straight signal path.
The analog input should be isolated from noisy signal traces
to avoid coupling of spurious signals into the input. Any ex-
ternal component (e.g., a filter capacitor) connected between
the converter's input and ground should be connected to a
very clean point in the analog ground plane.
where tr is the clock rise time and tPD is the propagation rate
of the signal along the trace, the CLOCK pin should be a.c.
terminated with a series RC to ground such that the resistor
value is equal to the characteristic impedance of the clock line
and the capacitor value is
where tPD is the signal propagation rate down the clock line,
"L" is the line length and Zo is the characteristic impedance of
the clock line. This termination should be located as close as
possible to, but within one centimeter of, the ADC08100 clock
pin. Typical tPD is about 150 ps/inch on FR-4 board material.
For FR-4 board material, the value of C becomes
where L is the length of the clock line in inches.
5.0 LAYOUT AND GROUNDING
Proper grounding and proper routing of all signals are essen-
tial to ensure accurate conversion. A combined analog and
digital ground plane should be used.
Since digital switching transients are composed largely of
high frequency components, total ground plane copper
weight will have little effect upon the logic-generated noise
because of the skin effect. Total surface area is more impor-
tant than is total ground plane volume. Capacitive coupling
between the typically noisy digital circuitry and the sensitive
FIGURE 5. Layout Example
Figure 5 gives an example of a suitable layout. All analog cir-
cuitry (input amplifiers, filters, reference components, etc.)
should be placed together away from any digital components.
6.0 DYNAMIC PERFORMANCE
The ADC08100 is AC tested and its dynamic performance is
guaranteed. To meet the published specifications, the clock
source driving the CLK input must exhibit less than 3 ps (rms)
of jitter. For best AC performance, isolating the ADC clock
from any digital circuitry should be done with adequate
buffers, as with a clock tree. See Figure 6.
It is good practice to keep the ADC clock line as short as pos-
sible and to keep it well away from any other signals. Other
signals can introduce jitter into the clock signal. The clock
signal can also introduce noise into the analog path.
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