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ADC08100 View Datasheet(PDF) - National ->Texas Instruments

Part NameDescriptionManufacturer
ADC08100 8-Bit, 20 Msps to 100 Msps, 1.3 mW/Msps A/D Converter National-Semiconductor
National ->Texas Instruments National-Semiconductor
ADC08100 Datasheet PDF : 20 Pages
First Prev 11 12 13 14 15 16 17 18 19 20
10137134
FIGURE 4. The input amplifier should incorporate some gain for best performance (see text).
The RC at the amplifier output filters the clock rate energy that
comes out of the analog input due to the input sampling circuit.
The optimum time constant for this circuit depends not only
upon the amplifier and ADC, but also on the circuit layout and
board material. A resistor value should be chosen between
18and 47and the capacitor value chose according to the
formula
The value of "C" in the formula above should include the ADC
input capacitance when the clock is high.
This will provide optimum SNR performance for Nyquist ap-
plications. Best THD performance is realized when the ca-
pacitor and resistor values are both zero, but this would
compromise SNR and SINAD performance. Generally, there
should be no resistor or capacitor between the ADC input and
any amplifier for undersampling applications.
The circuit of Figure 4 has both gain and offset adjustments.
If you eliminate these adjustments normal circuit tolerances
may cause signal clipping unless care is exercised in the
worst case analysis of component tolerance and the input
signal excursion is appropriately limited to account for the
worst case conditions. Of course, this means that the design-
er will not be able to depend upon getting a full scale output
with maximum signal input.
Full scale and offset adjustments may also be made by ad-
justing VRT and VRB, perhaps with the aid of a pair of DACs.
3.0 POWER SUPPLY CONSIDERATIONS
A/D converters draw sufficient transient current to corrupt
their own power supplies if not adequately bypassed. A
10 µF tantalum or aluminum electrolytic capacitor should be
placed within an inch (2.5 cm) of the A/D power pins, with a
0.1 µF ceramic chip capacitor placed within one centimeter of
the converter's power supply pins. Leadless chip capacitors
are preferred because they have low lead inductance.
While a single voltage source is recommended for the VA and
DR VD supplies of the ADC08100, these supply pins should
be well isolated from each other to prevent any digital noise
from being coupled into the analog portions of the ADC. A
choke or 27resistor is recommended between these supply
lines with adequate bypass capacitors close to the supply
pins.
As is the case with all high speed converters, the ADC08100
should be assumed to have little power supply rejection. None
of the supplies for the converter should be the supply that is
used for other digital circuitry in any system with a lot of digital
power being consumed. The ADC supplies should be the
same supply used for other analog circuitry.
No pin should ever have a voltage on it that is in excess of the
supply voltage or below ground by more than 300 mV, not
even on a transient basis. This can be a problem upon appli-
cation of power and power shut-down. Be sure that the sup-
plies to circuits driving any of the input pins, analog or digital,
do not come up any faster than does the voltage at the
ADC08100 power pins.
4.0 THE DIGITAL INPUT PINS
The ADC08100 has two digital input pins: The PD pin and the
Clock pin.
4.1 The PD Pin
The Power Down (PD) pin, when high, puts the ADC08100
into a low power mode where power consumption is reduced
to 1 mW. Output data is valid and accurate about 1 microsec-
ond after the PD pin is brought low.
The digital output pins retain the last conversion output code
when either the clock is stopped or the PD pin is high.
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