|ADC08100||8-Bit, 20 Msps to 100 Msps, 1.3 mW/Msps A/D Converter|
National ->Texas Instruments
|ADC08100 Datasheet PDF : 20 Pages |
APERTURE (SAMPLING) DELAY is that time required after
the fall of the clock input for the sampling switch to open. The
Sample/Hold circuit effectively stops capturing the input sig-
nal and goes into the “hold” mode tAD after the clock goes low.
APERTURE JITTER is the variation in aperture delay from
sample to sample. Aperture jitter shows up as input noise.
BOTTOM OFFSET is the difference between the input volt-
age that just causes the output code to transition to the first
code and the negative reference voltage. Bottom Offset is
defined as EOB = VZT – VRB, where VZT is the first code tran-
sition input voltage. VRB is the lower reference voltage. Note
that this is different from the normal Zero Scale Error.
CLOCK DUTY CYCLE is the ratio of the time that the clock
waveform is at a logic high to the total time of one clock period.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of
the maximum deviation from the ideal step size of 1 LSB.
Measured at 100 Msps with a ramp input.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE
BITS) is another method of specifying Signal-to-Noise and
Distortion Ratio, or SINAD. ENOB is defined as (SINAD –
1.76) / 6.02 and says that the converter is equivalent to a per-
fect ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH is a measure of the frequency
at which the reconstructed output fundamental drops 3 dB
below its low frequency value for a full scale input. The test is
performed with fIN equal to 100 kHz plus integer multiples of
fCLK. The input frequency at which the output is −3 dB relative
to the low frequency input signal is the full power bandwidth.
FULL-SCALE ERROR is a measure of how far the last code
transition is from the ideal 1½ LSB below VRT and is defined
Vmax + 1.5 LSB – VRT
where Vmax is the voltage at which the transition to the maxi-
mum (full scale) code occurs.
INTEGRAL NON-LINEARITY (INL) is a measure of the de-
viation of each individual code from a line drawn from zero
scale (½ LSB below the first code transition) through positive
full scale (½ LSB above the last code transition). The devia-
tion of any given code from this straight line is measured from
the center of that code value. The end point test method is
used. Measured at 100 Msps with a ramp input.
INTERMODULATION DISTORTION (IMD) is the creation of
additional spectral components as a result of two sinusoidal
frequencies being applied to the ADC input at the same time.
It is defined as the ratio of the power in the second and third
order intermodulation products to the power in one of the
original frequencies. IMD is usually expressed in dBFS.
MISSING CODE are those output codes that are skipped and
will never appear at the ADC outputs. These codes cannot be
reached with any input value.
OUTPUT DELAY is the time delay after the rising edge of the
input clock before the data update is present at the output
OUTPUT HOLD TIME is the length of time that the output data
is valid after the rise of the input clock.
PIPELINE DELAY (LATENCY) is the number of clock cycles
between initiation of conversion and when that data is pre-
sented to the output driver stage. New data is available at
every clock cycle, but the data lags the conversion by the
Pipeline Delay plus the Output Delay.
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in
dB, of the rms value of the input signal at the output to the rms
value of the sum of all other spectral components below one-
half the sampling frequency, not including harmonics or DC.
SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or
SINAD) is the ratio, expressed in dB, of the rms value of the
input signal at the output to the rms value of all of the other
spectral components below half the clock frequency, includ-
ing harmonics but excluding D.C.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the differ-
ence, expressed in dB, between the rms values of the input
signal at the output and the peak spurious signal, where a
spurious signal is any signal present in the output spectrum
that is not present at the input.
TOTAL HARMONIC DISTORTION (THD) is the ratio, ex-
pressed in dB, of the total of the first nine harmonic levels at
the output to the level of the fundamental at the output. THD
is calculated as
where F1 is the RMS power of the fundamental (input) fre-
quency and f2 through f10 is the power in the first 9 harmonics
in the output spectrum.
ZERO SCALE OFFSET ERROR is the error in the input volt-
age required to cause the first code transition. It is defined as
VOFF = VZT − VRB
where VZT is the first code transition input voltage.
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