74HCT107D View Datasheet(PDF) - NXP Semiconductors.
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Description
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74HCT107D Datasheet PDF : 18 Pages
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Nexperia
74HC107; 74HCT107
Dual JK flip-flop with reset; negative-edge trigger
Table 7. Dynamic characteristics …continued
GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 7
Symbol Parameter Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max
Min
Max
fmax
maximum
nCP input; see Figure 5
frequency
VCC = 4.5 V
30 66 -
24
-
20
- MHz
VCC = 5.0 V; CL = 15 pF
- 73 -
-
-
-
- MHz
CPD
power
per flip-flop;
[3] - 30 -
-
-
-
- pF
dissipation VI = GND to VCC 1.5 V
capacitance
[1] tpd is the same as tPHL, tPLH.
[2] tt is the same as tTHL, tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of outputs.
11. Waveforms
9,
Q-Q.
LQSXW
*1'
9,
Q&3LQSXW
*1'
92+
Q4RXWSXW
92/
92+
Q4RXWSXW
92/
90
WVX
WK
IPD[
WVX
90
W:
W3+/
90
W7+/
90
W3/+
W7/+
WK
W3/+
W7/+
W3+/
W7+/
DDE
Fig 5.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Clock propagation delays, pulse width, set-up and hold times, output transition times and the maximum
frequency
74HC_HCT107
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 30 November 2015
© Nexperia B.V. 2017. All rights reserved
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