Nexperia
74HC107; 74HCT107
Dual JK flip-flop with reset; negative-edge trigger
13. Abbreviations
Table 10. Abbreviations
Acronym
Description
CMOS
Complementary Metal-Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
TTL
Transistor-Transistor Logic
14. Revision history
Table 11. Revision history
Document ID
Release date Data sheet status
Change notice Supersedes
74HC_HCT107 v.5
Modifications:
20151130
Product data sheet
-
74HC_HCT107 v.4
• Type numbers 74HC107N and 74HCT107N (SOT27-1) removed.
74HC_HCT107 v.4
Modifications:
20150126
Product data sheet
-
74HC_HCT107 v.3
• Table 7: Power dissipation capacitance condition for 74HCT107 is corrected.
74HC_HCT107 v.3
Modifications:
20131118
Product data sheet
-
74HC_HCT107_CNV v.2
• The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
74HC_HCT107_CNV v.2 19901201
Product specification
-
-
74HC_HCT107
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 30 November 2015
© Nexperia B.V. 2017. All rights reserved
15 of 18