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SI5332 View Datasheet(PDF) - Silicon Laboratories

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Si5332 Data Sheet
Functional Description
Si5332: 6-Output, 32-QFN
CLKIN_2
CLKIN_2b
XTAL
Si5332A/B/C/D: External Crystal
Si5332E/F/G/H: Internal Crystal
SCLK
SDATA
Input1
Input2
Input3
Input4
Input5
OSC
÷INT
NVM
I2C
HW Input
Control
PLL
Multi
Synth
Multi
Synth
INT
INT
INT
INT
INT
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
VDDO0
OUT0
OUT0b
VDDO1
OUT1
OUT1b
VDDO2
OUT2
OUT2b
VDDO3
OUT3
OUT3b
VDDO4
OUT4
OUT4b
VDDO5
OUT5b
OUT5
Figure 3.3. Block Diagram for 6-Output Si5332 in 32-QFN
The Si5332 32-QFN features:
• Up to six differential clock outputs with individual VDDO.
• Five user-configurable HW input pins, defined using ClockBuilder Pro.
3.2 Modes of Operation
The Si5332 supports both free-run and synchronous modes of operation. The default mode selection is set in ClockBuilder Pro. Alterna-
tively, a universal hardware input pin can be defined as CLKIN_SEL to select between a crystal or clock input. There is also the option
to select the input source via the serial interface by writing to the input select register.
3.2.1 Initialization
Once power is applied, the device begins an initialization period where it downloads default register values and configuration data from
NVM and performs other initialization tasks. Communicating with the device through the serial interface is possible once this initializa-
tion period is complete. The clock outputs will be squelched until the device initialization is done.
3.3 Frequency Configuration
The phase-locked loop is fully integrated and does not require external loop filter components. Its function is to phase lock to the selec-
ted input and provide a common synchronous reference to the high-performance MultiSynth fractional or integer dividers.
A cross point mux connects any of the MultiSynth divided frequencies or INT divided frequencies to individual output drivers or banks of
output drivers. Additional output integer dividers provide further frequency division by an even integer from 1 to 63. The frequency con-
figuration of the device is programmed by setting the input dividers (P), the PLL feedback fractional divider (Mn/Md), the MultiSynth
fractional dividers (Nn/Nd), and the output integer dividers (R). Silicon Labs’ Clockbuilder Pro configuration utility determines the opti-
mum divider values for any desired input and output frequency plan
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