SI5332 View Datasheet(PDF) - Silicon Laboratories
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SI5332 Datasheet PDF : 69 Pages
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Si5332 Data Sheet
Electrical Specifications
Table 5.11. PCI-Express Clock Outputs (100 MHz HCSL)
(VDD = VDDA = 1.8 V to 3.3 V +10%/-5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C)
Parameter
Test Condition
SSC On/Off
Typ
Max
Units
PCIe Gen 1.1
Includes PLL BW 1.5–22 MHz,
Off
11
19
ps RMS
Peaking = 3dB, Td=10 ns,
On
22
30
ps RMS
Ftrk=1.5 MHz with BER = 1E-12 2
PCIe Gen 2.1
Includes PLL BW 5MHz & 8–16 MHz,
Off
0.12
0.17 ps RMS
Jitter Peaking = 0.01-1 dB & 3 dB,
On
0.8
1.3
ps RMS
Td=12ns, Low Band, F < 1.5 MHz
Includes PLL BW 5 MHz & 8–16 MHz,
Off
0.016 0.023 ps RMS
Jitter Peaking = 0.01-1dB & 3dB,
On
0.12
0.21 ps RMS
Td=12ns, High Band, 1.5 MHz < F < Nyquist2
PCIe Gen 3.0 Com-
mon Clock
Includes PLL BW 2–4 MHz & 5 MHz, Peaking =
0.01-2dB & 1dB,
Td=12 ns, CDR = 10 MHz 2, 3
Off
0.037 0.048 ps RMS
On
0.26
0.34 ps RMS
PCIe Gen3.0 SRIS
Includes PLL BW 4 MHz
On
0.35
0.41 ps RMS
Peaking = 2dB & 1dB, Td=12 ns
CDR = 10 MHz 2, 3
PCIe Gen 4.0 Com-
mon Clock
Includes PLL BW 2–4 MHz & 5 MHz, Peaking =
0.01-2dB & 1dB,
Td=12 ns, CDR = 10 MHz 2, 3
Off
0.037 0.048 ps RMS
On
0.26
0.34 ps RMS
PCIe Gen4.0 SRIS
Includes PLL BW 4 MHz
On
0.37
0.42 ps RMS
Peaking = 2dB & 1dB, Td=12 ns
CDR = 10 MHz 2, 3
Notes:
1. All jitter data in this table is based upon all output formats being differential. When LVCMOS outputs are used, there is the poten-
tial that the output jitter may increase due to the nature of LVCMOS outputs. If your configuration implements any LVCMOS out-
put and any output is required to have jitter less than 3 ps RMS, contact Silicon Labs for support to validate your configuration
and ensure the best jitter performance.
2. All output clocks 100 MHz HCSL format. Jitter data taken from Clock Jitter Tool v.1.3.
3. Excludes oscilloscope sampling noise.
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