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ADC0803LCN View Datasheet(PDF) - Renesas Electronics

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ADC0803LCN Datasheet PDF : 17 Pages
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ADC0803, ADC0804
Analog Differential Voltage Inputs and Common-
Mode Rejection
This A/D gains considerable applications flexibility from the
analog differential voltage input. The VlN(-) input (pin 7) can be
used to automatically subtract a fixed voltage value from the
input reading (tare correction). This is also useful in 4mA -
20mA current loop conversion. In addition, common-mode
noise can be reduced by use of the differential input.
The time interval between sampling VIN(+) and VlN(-) is 41/2
clock periods. The maximum error voltage due to this slight time
difference between the input voltage samples is given by:
VE MAX
=
VPEAK2fCM
---4---.--5----
fCLK
where:
VE is the error voltage due to sampling delay,
VPEAK is the peak value of the common-mode voltage,
fCM is the common-mode frequency.
For example, with a 60Hz common-mode frequency, fCM, and a
640kHz A/D clock, fCLK, keeping this error to 1/4 LSB (~5mV)
would allow a common-mode voltage, VPEAK, given by:
VPEAK
=
-------V-----E------M----A----X--------f-C-----L---K-------
2 fC M   4.5
,
or
VPEAK
=
---5----------1---0------3---------6---4---0----------1---0----3---
6.28   60   4.5
1.9 V
.
The allowed range of analog input voltage usually places more
severe restrictions on input common-mode voltage levels than
this.
An analog input voltage with a reduced span and a relatively
large zero offset can be easily handled by making use of the
differential input (see Reference Voltage Span Adjust).
Analog Input Current
The internal switching action causes displacement currents to
flow at the analog inputs. The voltage on the on-chip
capacitance to ground is switched through the analog differential
input voltage, resulting in proportional currents entering the
VIN(+) input and leaving the VIN(-) input. These current
transients occur at the leading edge of the internal clocks. They
rapidly decay and do not inherently cause errors as the on-chip
comparator is strobed at the end of the clock perIod.
Input Bypass Capacitors
Bypass capacitors at the inputs will average these charges and
cause a DC current to flow through the output resistances of the
analog signal sources. This charge pumping action is worse for
continuous conversions with the VIN(+) input voltage at full
scale. For a 640kHz clock frequency with the VIN(+) input at 5V,
this DC current is at a maximum of approximately 5A.
Therefore, bypass capacitors should not be used at the
analog inputs or the VREF/2 pin for high resistance sources
(>1k). If input bypass capacitors are necessary for noise
FN3094 Rev 4.00
August 2002
filtering and high source resistance is desirable to minimize
capacitor size, the effects of the voltage drop across this input
resistance, due to the average value of the input current, can be
compensated by a full scale adjustment while the given source
resistor and input bypass capacitor are both in place. This is
possible because the average value of the input current is a
precise linear function of the differential input voltage at a
constant conversion rate.
Input Source Resistance
Large values of source resistance where an input bypass
capacitor is not used will not cause errors since the input
currents settle out prior to the comparison time. If a low- pass
filter is required in the system, use a low-value series resistor
(1k) for a passive RC section or add an op amp RC active
low-pass filter. For low-source-resistance applications (1k),
a 0.1F bypass capacitor at the inputs will minimize EMI due to
the series lead inductance of a long wire. A 100series
resistor can be used to isolate this capacitor (both the R and C
are placed outside the feedback loop) from the output of an op
amp, if used.
Stray Pickup
The leads to the analog inputs (pins 6 and 7) should be kept as
short as possible to minimize stray signal pickup (EMI). Both
EMI and undesired digital-clock coupling to these inputs can
cause system errors. The source resistance for these inputs
should, in general, be kept below 5k. Larger values of source
resistance can cause undesired signal pickup. Input bypass
capacitors, placed from the analog inputs to ground, will
eliminate this pickup but can create analog scale errors as these
capacitors will average the transient input switching currents of
the A/D (see Analog Input Current). This scale error depends on
both a large source resistance and the use of an input bypass
capacitor. This error can be compensated by a full scale
adjustment of the A/D (see Full Scale Adjustment) with the
source resistance and input bypass capacitor in place, and the
desired conversion rate.
Reference Voltage Span Adjust
For maximum application flexibility, these A/Ds have been
designed to accommodate a 5V, 2.5V or an adjusted voltage
reference. This has been achieved in the design of the IC as
shown in Figure 12.
Notice that the reference voltage for the IC is either 1/2 of the
voltage which is applied to the V+ supply pin, or is equal to the
voltage which is externally forced at the VREF/2 pin. This
allows for a pseudo-ratiometric voltage reference using, for the
V+ supply, a 5V reference voltage. Alternatively, a voltage less
than 2.5V can be applied to the VREF/2 input. The internal gain
to the VREF/2 input is 2 to allow this factor of 2 reduction in the
reference voltage.
Such an adjusted reference voltage can accommodate a
reduced span or dynamic voltage range of the analog input
voltage. If the analog input voltage were to range from 0.5V to
3.5V, instead of 0V to 5V, the span would be 3V. With 0.5V
Page 9 of 17
 

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