ADC0804 View Datasheet(PDF) - Renesas Electronics
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ADC0804 Datasheet PDF : 17 Pages
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ADC0803, ADC0804
Understanding A/D Error Specs
A perfect A/D transfer characteristic (staircase wave-form) is
shown in Figure 11A. The horizontal scale is analog input
voltage and the particular points labeled are in steps of 1 LSB
(19.53mV with 2.5V tied to the VREF/2 pin). The digital output
codes which correspond to these inputs are shown as D-1, D,
and D+1. For the perfect A/D, not only will center-value (A - 1,
A, A + 1, . . .) analog inputs produce the correct output digital
codes, but also each riser (the transitions between adjacent
output codes) will be located 1/2 LSB away from each center-
value. As shown, the risers are ideal and have no width.
Correct digital output codes will be provided for a range of
analog input voltages which extend 1/2 LSB from the ideal
center-values. Each tread (the range of analog input voltage
which provides the same digital output code) is therefore 1
LSB wide.
The error curve of Figure 11B shows the worst case transfer
function for the ADC080X. Here the specification guarantees
that if we apply an analog input equal to the LSB analog
voltage center-value, the A/D will produce the correct digital
code.
Next to each transfer function is shown the corresponding error
plot. Notice that the error includes the quantization uncertainty
of the A/D. For example, the error at point 1 of Figure 11A is
+1/2 LSB because the digital code appeared 1/2 LSB in
advance of the center-value of the tread. The error plots
always have a constant negative slope and the abrupt upside
steps are always 1 LSB in magnitude, unless the device has
missing codes.
Detailed Description
The functional diagram of the ADC080X series of A/D
converters operates on the successive approximation principle
(see Application Notes AN016 and AN020 for a more detailed
description of this principle). Analog switches are closed
sequentially by successive-approximation logic until the analog
differential input voltage [VlN(+) - VlN(-)] matches a voltage
derived from a tapped resistor string across the reference
voltage. The most significant bit is tested first and after 8
comparisons (64 clock cycles), an 8-bit binary code (1111
1111 = full scale) is transferred to an output latch.
The normal operation proceeds as follows. On the high-to-low
transition of the WR input, the internal SAR latches and the shift-
register stages are reset, and the INTR output will be set high.
As long as the CS input and WR input remain low, the A/D will
remain in a reset state. Conversion will start from 1 to 8 clock
periods after at least one of these inputs makes a low-to-high
transition. After the requisite number of clock pulses to complete
the conversion, the INTR pin will make a high-to-low transition.
This can be used to interrupt a processor, or otherwise signal
the availability of a new conversion. A RD operation (with CS
low) will clear the INTR line high again. The device may be
operated in the free-running mode by connecting INTR to the
WR input with CS = 0. To ensure start-up under all possible
FN3094 Rev 4.00
August 2002
conditions, an external WR pulse is required during the first
power-up cycle. A conversion-in-process can be interrupted by
issuing a second start command.
Digital Operation
The converter is started by having CS and WR simultaneously
low. This sets the start flip-flop (F/F) and the resulting “1” level
resets the 8-bit shift register, resets the Interrupt (INTR) F/F and
inputs a “1” to the D flip-flop, DFF1, which is at the input end of
the 8-bit shift register. Internal clock signals then transfer this “1”
to the Q output of DFF1. The AND gate, G1, combines this “1”
output with a clock signal to provide a reset signal to the start
F/F. If the set signal is no longer present (either WR or CS is a
“1”), the start F/F is reset and the 8-bit shift register then can
have the “1” clocked in, which starts the conversion process. If
the set signal were to still be present, this reset pulse would
have no effect (both outputs of the start F/F would be at a “1”
level) and the 8-bit shift register would continue to be held in the
reset mode. This allows for asynchronous or wide CS and WR
signals.
After the “1” is clocked through the 8-bit shift register (which
completes the SAR operation) it appears as the input to DFF2.
As soon as this “1” is output from the shift register, the AND
gate, G2, causes the new digital word to transfer to the Three-
State output latches. When DFF2 is subsequently clocked, the
Q output makes a high-to-low transition which causes the INTR
F/F to set. An inverting buffer then supplies the INTR output
signal.
When data is to be read, the combination of both CS and RD
being low will cause the INTR F/F to be reset and the three-
state output latches will be enabled to provide the 8-bit digital
outputs.
Digital Control Inputs
The digital control inputs (CS, RD, and WR) meet standard TTL
logic voltage levels. These signals are essentially equivalent to
the standard A/D Start and Output Enable control signals, and
are active low to allow an easy interface to microprocessor
control busses. For non-microprocessor based applications, the
CS input (pin 1) can be grounded and the standard A/D Start
function obtained by an active low pulse at the WR input (pin 3).
The Output Enable function is achieved by an active low pulse at
the RD input (pin 2).
Analog Operation
The analog comparisons are performed by a capacitive charge
summing circuit. Three capacitors (with precise ratioed values)
share a common node with the input to an auto-zeroed
comparator. The input capacitor is switched between VlN(+) and
VlN(-), while two ratioed reference capacitors are switched
between taps on the reference voltage divider string. The net
charge corresponds to the weighted difference between the
input and the current total value set by the successive
approximation register. A correction is made to offset the
comparison by 1/2 LSB (see Figure 11A).
Page 8 of 17
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