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ADC0804LCN View Datasheet(PDF) - Renesas Electronics

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ADC0804LCN Datasheet PDF : 17 Pages
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ADC0803, ADC0804
Electrical Specifications (Notes 2, 8) (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
DC DIGITAL LEVELS AND DC SPECIFICATIONS V+ = 5V, and TMIN to TMAX, Unless Otherwise Specified
CONTROL INPUTS (Note 7)
Logic “1“ Input Voltage (Except Pin 4 CLK V+ = 5.25V
IN), VINH
Logic “0“ Input Voltage (Except Pin 4 CLK V+ = 4.75V
IN), VINL
CLK IN (Pin 4) Positive Going Threshold
Voltage, V+CLK
CLK IN (Pin 4) Negative Going Threshold
Voltage, V-CLK
CLK IN (Pin 4) Hysteresis, VH
Logic “1” Input Current (All Inputs), IINHI VlN = 5V
Logic “0” Input Current (All Inputs), IINLO VlN = 0V
Supply Current (Includes Ladder Current), I+ fCLK = 640kHz, TA = 25oC and CS = Hl
DATA OUTPUTS AND INTR
2.0
-
V+
V
-
-
0.8
V
2.7
3.1
3.5
V
1.5
1.8
2.1
V
0.6
1.3
2.0
V
-
0.005
1

-1
-0.005
-
A
-
1.3
2.5
mA
Logic “0” Output Voltage, VOL
Logic “1” Output Voltage, VOH
Three-State Disabled Output Leakage (All
Data Buffers), ILO
Output Short Circuit Current, ISOURCE
Output Short Circuit Current, ISINK
NOTES:
lO = 1.6mA, V+ = 4.75V
lO = -360A, V+ = 4.75V
VOUT = 0V
VOUT = 5V
VOUT Short to GND, TA = 25oC
VOUT Short to V+, TA = 25oC
-
-
0.4
V
2.4
-
-
V
-3
-
-
A
-
-
3
A
4.5
6
-
mA
9.0
16
-
mA
2. All voltages are measured with respect to GND, unless otherwise specified. The separate AGND point should always be wired to the DGND,
being careful to avoid ground loops.
3. For VIN(-) VIN(+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input (see Block Diagram) which will
forward conduct for analog input voltages one diode drop below ground or one diode drop greater than the V+ supply. Be careful, during testing
at low V+ levels (4.5V), as high level analog inputs (5V) can cause this input diode to conduct - especially at elevated temperatures, and cause
errors for analog inputs near full scale. As long as the analog VIN does not exceed the supply voltage by more than 50mV, the output code will
be correct. To achieve an absolute 0V to 5V input voltage range will therefore require a minimum supply voltage of 4.950V over temperature
variations, initial tolerance and loading.
4. With V+ = 6V, the digital logic interfaces are no longer TTL compatible.
5. With an asynchronous start pulse, up to 8 clock periods may be required before the internal clock phases are proper to start the conversion process.
6. The CS input is assumed to bracket the WR strobe input so that timing is dependent on the WR pulse width. An arbitrarily wide pulse width will
hold the converter in a reset mode and the start of conversion is initiated by the low to high transition of the WR pulse (see Timing Diagrams).
7. CLK IN (pin 4) is the input of a Schmitt trigger circuit and is therefore specified separately.
8. None of these A/Ds requires a zero-adjust. However, if an all zero code is desired for an analog input other than 0V, or if a narrow full scale span exists
(for example: 0.5V to 4V full scale) the VIN(-) input can be adjusted to achieve this. See the Zero Error description in this data sheet.
Timing Waveforms
V+
RD
CS
DATA
OUTPUT
CL 10K
FIGURE 1A. t1H
2.4V
RD
0.8V
VOH
DATA
OUTPUTS
GND
tr = 20ns
tr
90%
50%
10%
t1H
90%
FIGURE 1B. t1H, CL = 10pF
FN3094 Rev 4.00
August 2002
Page 4 of 17
 

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