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AR9271 Datasheet PDF : 152 Pages
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6.2.12 Reset Status Register .................. 47
6.2.13 Chip Revision ID
(RST_REVISION_ID) ................. 47
6.3 USB Controller DMA Registers ........... 48
6.3.1 Interrupt Status Register
(USB_DMA_INTERRUPT) ........ 48
6.3.2 Interrupt Mask Register
(USB_DMA_INTERRUPT_MASK)
49
6.3.3 USB Rx Chain 0 Descriptor Start
Address Register
(USB_DMA_RX_0_DESC_START_
ADDRESS) ................................... 49
6.3.4 USB Rx Chain 0 DMA Start Register
(USB_DMA_RX_0_DMA_START)
50
6.3.5 USB Rx Chain 0 AHB Burst Size
Register
(USB_DMA_RX_0_BURST_SIZE)
50
6.3.6 USB Rx Chain 0 Packet Offset
Register
(USB_DMA_RX_0_PKT_OFFSET)
50
6.3.7 Rx Chain 0 Data Swap Register
(USB_RX_0_DATA_SWAP) ...... 50
6.3.8 USB Rx Chain 1 Descriptor Start
Address Register
(USB_DMA_RX_1_DESC_START_
ADDRESS) ................................... 50
6.3.9 USB Rx Chain 1 DMA Start Register
(USB_DMA_RX_1_DMA_START)
51
6.3.10 USB Rx Chain 1 AHB Burst Size
Register
(USB_DMA_RX_1_BURST_SIZE)
51
6.3.11 USB Rx Chain 1 Packet Offset
Register
(USB_DMA_RX_1_PKT_OFFSET)
51
6.3.12 Rx Chain 1 Data Swap Register
(USB_RX_DATA_SWAP) .......... 51
6.3.13 USB Rx Chain 2 Descriptor Start
Address Register
(USB_DMA_RX_2_DESC_START_
ADDRESS) ................................... 52
6.3.14 USB Rx Chain 2 DMA Start Register
(USB_DMA_RX_2_DMA_START)
52
6.3.15 USB Rx Chain 2 AHB Burst Size
Register
(USB_DMA_RX_2_BURST_SIZE)
52
6.3.16 USB Rx Chain 2 Packet Offset
Register
(USB_DMA_RX_2_PKT_OFFSET)
52
6.3.17 Rx Chain 2 Data Swap Register
(USB_RX_2_DATA_SWAP) ...... 52
6.3.18 USB Tx Chain 0 Descriptor Start
Address Register
(USB_DMA_TX_0_DESC_START_
ADDRESS) ................................... 53
6.3.19 USB Tx Chain 0 DMA Start Register
(USB_DMA_TX_0_DMA_START)
53
6.3.20 USB Tx Chain 0 Interrupt Limit
Register
(USB_DMA_TX_0_INTERRUPT_LI
MIT) .............................................. 53
6.3.21 Tx Chain 0 AHB Burst Size Register
(USB_DMA_TX_0_BURST_SIZE)
53
6.3.22 Tx Chain 0 Data Swap Register
(USB_TX_0_DATA_SWAP) ...... 53
6.4 SPI Control Registers ............................ 54
SPI Control Register Notes 54
6.4.1 SPI Control/Status Register
(SPI_CS) ....................................... 55
6.4.2 SPI Address/Opcode Register
(SPI_AO) ...................................... 55
6.4.3 SPI Data Register (SPI_D) ......... 56
MAC Register Descriptions 57
6.5 General DMA and Rx-Related Registers
57
6.5.1 Command (CR) ........................... 58
6.5.2 Rx Queue Descriptor Pointer
(RXDP) ......................................... 58
6.5.3 Configuration and Status (CFG) 59
6.5.4 Maximum Interrupt Rate Threshold
(MIRT) .......................................... 60
6.5.5 Interrupt Global Enable (IER) ... 60
6.5.6 Tx Interrupt Mitigation Thresholds
(TIMT) .......................................... 60
6.5.7 Rx Interrupt Mitigation Thresholds
(RIMT) .......................................... 61
4 AR9271 Single-Chip 1x1 MAC/BB/Radio for 802.11n WLANs
4 November 2011
Atheros Communications, Inc.
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