AR9271 View Datasheet(PDF) - Unspecified
Part Name
Description
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AR9271 Datasheet PDF : 152 Pages
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4
JTAG_SEL
R
0x0 If set, denotes the CPU JTAG interface. Otherwise, it is a normal
JTAG interface.
3:1
RES
R
0x0 Reserved. Must be written with zero. Contains zeros when read.
0
EXT_BOOT
R
0x0 Used to denote where the chip boots.
0 Boot from the internal EEPROM
1 Boot from the external SPI Flash
6.2.7 Watchdog Timer Interrupt (RST_WATCHDOG_INT)
Address: 0x0005_001C
Access: Read-Only
This register contains the interrupt status of the
watchdog timer.
Bit
Bit Name Type Reset Description
31:1
RES
R
0x0 Reserved. Must be written with zero. Contains zeros when read.
0
WATCHDOG_ R
0x0 Indicates the watchdog timer has expired
INT
6.2.8 General Timer Interrupt (RST_GENERAL_TIMER_INT)
Address: 0x0005_0004
Access: Read-Only
This register indicates that the general timer
has expired.
Bit
Bit Name Type Reset Description
31:1
RES
R
0x0 Reserved. Must be written with zero. Contains zeros when read.
0
GTMR_INT
R
0x0 Indicates the general timer has expired
6.2.9 Clock Control Register
Address: 0x0005_0040
Access: Read/Write
This register is used to configure the clock
settings for the AR9271.
Bit
31:14
13:12
11:9
8
7:5
Bit Name
RES
AHB_DIVIDE
RES
SPI_SEL
RES
Type
R
R/W
R
R/W
R
Reset Description
0x0 Reserved. Must be written with zero. Contains zeros when read.
0x0 AHB clock frequency division ratio (AHB Clock/CPU Clock)
00 1/1
01 1/2
10 1/4
0x0 Reserved. Must be written with zero. Contains zeros when read.
0x0 Used to switch the function of I/O pins 18-21 between GPIO and
SPI
0 Sets the pins as GPIO 5-8
1 Sets the pins as SPI
0x0 Reserved. Must be written with zero. Contains zeros when read.
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
AR9271 Single-Chip 1x1 MAC/BB/Radio for 802.11n WLANs • 43
November 2011 • 43
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