SY10E112JITR(1998) View Datasheet(PDF) - Micrel
Part Name
Description
View to exact match
SY10E112JITR Datasheet PDF : 4 Pages
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QUAD
DRIVER
SY10E112
SY100E112
FEATURES
s 600ps max. propagation delay
s Extended 100E VEE range of –4.2V to –5.5V
s Common enable input
s Fully compatible with industry standard 10KH, 100K
I/O levels
s Internal 75KΩ input pulldown resistors
s Fully compatible with Motorola MC10E/100E112
s Available in 28-pin PLCC package
DESCRIPTION
The SY10/100E112 are quad drivers designed for use
in new, high-performance ECL systems. The E112 has two
pairs of OR/NOR outputs from each gate and a common,
buffered enable input. The data input can also be used as
an ECL memory address fan-out driver, although the E111
is designed specifically for this purpose, and offers lower
skew than the E112. For memory address driver applications
where scan capabilities are required, please refer to the
SY10/100E212 device.
BLOCK DIAGRAM
D0
D1
D2
D3
EN
PIN CONFIGURATION
Q0a
Q0b
Q0a
Q0b
VCCO
25 24 23 22 21 20 19
26
18
Q2b
Q1a
D3 27
17 Q2a
Q1b
D2 28
PLCC
16 VCC
VEE
1
TOP VIEW
15 Q1b
Q1a
D1
2
J28-1
14 Q1a
Q1b
D0
3
13 Q1b
Q2a
EN 4
12 Q1a
5 6 7 8 9 10 11
Q2b
Q2a
Q2b
Q3a
Q3b
Q3a
PIN NAMES
Q3b
Pin
D0-D3
EN
Qna, Qnb
Qna, Qnb
VCCO
Function
Data Inputs
Enable Input
True Outputs
Inverting Outputs
VCC to Output
Rev.: D Amendment: /2
1
Issue Date: May, 1998
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