|Y2554||5-V, 12-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN|
|Y2554 Datasheet PDF : 50 Pages |
5-V, 12-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN
SLAS220A –JUNE 1999
When the converter is using normal sampling, the sampling period is programmable. It can be 12 SCLKs (short
sampling) or 24 SCLKs (long sampling). Long sampling helps the input analog signal sampled to settle to 0.5
LSB accuracy when input source resistance is high.
An asynchronous (to the SCLK) signal, via dedicated hardware pin CSTART, can be used in order to have total
control of the sampling period and the start of a conversion. This is extended sampling. The falling edge of
CSTART is the start of the sampling period. The rising edge of CSTART is the end of the sampling period and
the start of the conversion. This function is useful for an application that requires:
D The use of an extended sampling period to accommodate different input source impedance.
D The use of a faster I/O clock on the serial port but not enough sampling time is available due to the fixed
number of SCLKs. This could be due to a high input source impedance or due to higher MUX ON resistance
at lower supply voltage (refer to application information).
Once the conversion is complete, the processor can initiate a read cycle using either the read FIFO command
to read the conversion result or simply select the next channel number for conversion. Since the device has a
valid conversion result in the output buffer, the conversion result is simply presented at the serial data output.
TLC2554/TLC2558 conversion modes
The TLC2554 and TLC2558 have four different conversion modes (mode 00, 01, 10, 11). The operation of each
mode is slightly different, depending on how the converter performs the sampling and which host interface is
used. The trigger for a conversion can be an active CSTART (extended sampling), CS (normal sampling, SPI
interface), or FS (normal sampling, TMS320 DSP interface). When FS is used as the trigger, CS can be held
active, i.e. CS does not need to be toggled through the trigger sequence. Different types of triggers should not
be mixed throughout the repeat and sweep operations. When CSTART is used as the trigger, the conversion
starts on the rising edge of CSTART. The minimum low time for CSTART is 800 ns. If an active CS or FS is used
as the trigger, the conversion is started after the 16th or 28th SCLK edge. Enough time (for conversion) should
be allowed between consecutive triggers so that no conversion is terminated prematurely.
one shot mode (mode 00)
One shot mode (mode 00) does not use the FIFO, and the EOC is generated as the conversion is in progress
(or INT is generated after the conversion is done).
repeat mode (mode 01)
Repeat mode (mode 01) uses the FIFO. Once the programmed FIFO threshold is reached, the FIFO must be
read, or the data is lost and the sequence starts over again. This allows the host to set up the converter and
continue monitoring a fixed input and come back to get a set of samples when preferred. The first conversion
must start with a select command so an analog input channel can be selected.
sweep mode (mode 10)
Sweep mode (mode 10) also uses the FIFO. Once it is programmed in this mode, all of the channels listed in
the selected sweep sequence are visited in sequence. The results are converted and stored in the FIFO. This
sweep sequence may not be completed if the FIFO threshold is reached before the list is completed. This allows
the system designer to change the sweep sequence length. Once the FIFO has reached its programmed
threshold, an interrupt (INT) is generated. The host must issue a read FIFO command to read and clear the FIFO
before the next sweep can start.
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