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Y2554 View Datasheet(PDF) - Texas Instruments

Part NameDescriptionManufacturer
Y2554 5-V, 12-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN Texas-Instruments
Texas Instruments Texas-Instruments
Y2554 Datasheet PDF : 50 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
TLC2554, TLC2558
5-V, 12-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN
SLAS220A –JUNE 1999
converter (continued)
SC
512
Node
512
256
REF+
8
REF+
4
REF+
2
REF+
1
REF+
1
REF+
Threshold
Detector
To Output
Latch
2-Bit
R-String
DAC
REF–
REF–
REF–
REF–
REF–
REF–
ST
ST
ST
ST
ST
ST
ST
VI
Figure 1. Simplified Model of the Successive-Approximation System
In the next phase of the conversion process the threshold detector begins identifying bits by identifying the
charge (voltage) on each capacitor relative to the reference (REFM) voltage. In the switching sequence, ten
capacitors are examined separately until all ten bits are identified and the charge-convert sequence is repeated.
In the first step of the conversion phase, the threshold detector looks at the first capacitor (weight = 512). Node
512 of this capacitor is switched to the REFP voltage, and the equivalent nodes of all the other capacitors on
the ladder are switched to REFM. If the voltage at the summing node is greater than the trip point of the threshold
detector (approximately one-half the VCC voltage), a bit 0 is placed in the output register and the 512-weight
capacitor is switched to REFM. If the voltage at the summing node is less than the trip point of the threshold
detector, a bit 1 is placed in the register. The 512-weight capacitor remains connected to REFP through the
remainder of the successive-approximation process. The process is repeated for the 1024-weight capacitor,
the 128-weight capacitor, and so forth down the line until all bits are counted.
With each step of the successive-approximation process, the initial charge is redistributed among the
capacitors. The conversion process relies on charge redistribution to count and weigh the bits from MSB to LSB.
serial interface
MSB
D15–D12
Command
INPUT DATA FORMAT
D11–D0
Configuration data field
LSB
Input data is binary. All trailing blanks can be filled with zeros.
OUTPUT DATA FORMAT READ CFR
MSB
D15–D12
D11–D0
Don’t care
Register content
LSB
OUTPUT DATA FORMAT CONVERSION/READ FIFO
MSB
LSB
D15–D4
D3–D0
Conversion result
All zeros
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5
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