|Y2554||5-V, 12-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN|
|Y2554 Datasheet PDF : 50 Pages |
5-V, 12-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN
SLAS220A –JUNE 1999
I Analog signal inputs. The analog inputs are applied to these terminals and are internally
multiplexed. The driving source impedance should be less than or equal to 1 kΩ.
For a source impedance greater than 1 kΩ, use the asynchronous conversion start signal CSTART
(CSTART low time controls the sampling period) or program long sampling period to increase the
I Chip select. A high-to-low transition on the CS input resets the internal 4-bit counter, enables SDI,
and removes SDO from 3-state within a maximum setup time. SDI is disabled within a setup time
after the 4-bit counter counts to 16 (clock edges) or a low-to-high transition of CS whichever
happens first. SDO is 3-stated after the rising edge of CS.
CS can be used as the FS pin when a dedicated serial port is used.
I This terminal controls the start of sampling of the analog input from a selected multiplex channel.
A high-to-low transition starts sampling of the analog input signal. A low-to-high transition puts the
S/H in hold mode and starts the conversion. This input is independent from SCLK and works when
CS is high (inactive). The low time of CSTART controls the duration of the sampling period of the
converter (extended sampling).
Tie this terminal to VCC if not used.
O End of conversion or interrupt to host processor.
[PROGRAMMED AS EOC]: This output goes from a high-to-low logic level at the end of the
sampling period and remains low until the conversion is complete and data are ready for transfer.
EOC is used in conversion mode 00 only.
[PROGRAMMED AS INT]: This pin can also be programmed as an interrupt output signal to the
host processor. The falling edge of INT indicates data are ready for output. The following CS↓ or
FS↑ clears INT. The falling edge of INT puts SDO back to 3-state even if CS is still active.
I DSP frame sync input. Indication of the start of a serial data frame in or out of the device. If FS
remains low at the falling edge of CS, SDI is not enabled. A high-to-low transition on the FS input
resets the internal 4-bit counter and enables SDI within a maximum setup time. SDI is disabled
within a setup time after the 4-bit counter counts to 16 (clock edges) or a low-to-high transition of
CS whichever happens first. SDO is 3-stated after the 16th bit is presented.
Tie this terminal to VCC if not used.
I Ground return for the internal circuitry. Unless otherwise noted, all voltage measurements are with
respect to GND.
I Both analog and reference circuits are powered down when this pin is at logic zero. The device can
be restarted by active CS or CSTART after this pin is pulled back to logic one.
I Input serial clock. This terminal receives the serial SCLK from the host processor. SCLK is used
to clock the input SDI to the input register. It is also used as the source of the conversion clock.
I Serial data input. The input data is presented with the MSB (D15) first. The first 4-bit MSBs,
D(15–12) are decoded as one of the 16 commands (12 only for the TLC2554). All trailing blanks
are filled with zeros. The configure write commands require an additional 12 bits of data.
When FS is not used (FS =1), the first MSB (D15) is expected after the falling edge of CS and is
shifted in on the rising edges of SCLK (after CS↓).
When FS is used (typical with an active FS from a DSP) the first MSB (D15) is expected after the
falling edge of FS and is shifted in on the falling edges of SCLK.
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