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TLV2541 View Datasheet(PDF) - Texas Instruments

Part NameDescriptionManufacturer
TLV2541 2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN Texas-Instruments
Texas Instruments Texas-Instruments
TLV2541 Datasheet PDF : 32 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
TLV2541, TLV2542, TLV2545
2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
SLAS245E MARCH 2000 REVISED APRIL 2010
Terminal Functions
TLV2541
TERMINAL
I/O
NAME NO.
DESCRIPTION
AIN
4 I Analog input channel
CS
1 I Chip select. A high-to-low transition on the CS input removes SDO from 3-state within a maximum setup time.
CS can be used as the FS pin when a dedicated DSP serial port is used.
FS
GND
7
I DSP frame sync input. Indication of the start of a serial data frame. Tie this terminal to VDD if not used.
3 I Ground return for the internal circuitry. Unless otherwise noted, all voltage measurements are with respect to GND.
SCLK
5 I Output serial clock. This terminal receives the serial SCLK from the host processor.
SDO
8 O The 3-state serial output for the A/D conversion result. SDO is kept in the high-impedance state until CS falling edge
or FS rising edge, whichever occurs first. The output format is MSB first.
When FS is not used (FS = 1 at the falling edge of CS): The MSB is presented to the SDO pin after CS falling edge
and output data is valid on the first falling edge of SCLK.
When CS and FS are both used (FS = 0 at the falling edge of CS): The MSB is presented to the SDO pin after the
falling edge of CS. When CS is tied/held low, the MSB is presented on SDO after the rising FS. Output data is valid
on the first falling edge of SCLK. (This is typically used with an active FS from a DSP using a dedicated serial port.)
VDD
VREF
6 I Positive supply voltage
2 I External reference input
TLV2542/45
TERMINAL
I/O
NAME NO.
DESCRIPTION
AIN0 /AIN(+) 4 I Analog input channel 0 for TLV2542—Positive input for TLV2545.
AIN1/AIN () 5 I Analog input channel 1 for TLV2542—Inverted input for TLV2545.
CS
1 I Chip select. A high-to-low transition on CS removes SDO from 3-state within a maximum delay time. This pin can
be connected to the frame sync of a DSP using a dedicated serial port.
GND
3 I Ground return for the internal circuitry. Unless otherwise noted, all voltage measurements are with respect to GND.
SCLK
7 I Output serial clock. This terminal receives the serial SCLK from the host processor.
SDO
8 O The 3-state serial output for the A/D conversion result. SDO is kept in the high-impedance state when CS is high
and presents output data after the CS falling edge until the LSB is presented. The output format is MSB first. SDO
returns to the Hi-Z state after the 16th SCLK. Output data is valid on the falling SCLK edge.
VDD
VREF
6 I Positive supply voltage
2 I External reference input
detailed description
The TLV2541, TLV2542, and TLV2545 are successive approximation (SAR) ADCs utilizing a charge
redistribution DAC. Figure 1 shows a simplified version of the ADC.
The sampling capacitor acquires the signal on AIN during the sampling period. When the conversion process
starts, the SAR control logic and charge redistribution DAC are used to add and subtract fixed amounts of charge
from the sampling capacitor to bring the comparator into a balanced condition. When the comparator is
balanced, the conversion is complete and the ADC output code is generated.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
3
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