Introduction
Note
Some instruction codes are not defined but do not cause the Undefined instruction trap
to be taken, for instance a multiply instruction with bit 6 changed to a 1. These
instructions must not be used because their action might change in future ARM
implementations. The behavior of these instruction codes on the ARM7TDMI
processor is unpredictable.
1.4.2
ARM instruction summary
The ARM instruction set summary is listed in Table 1-2.
Table 1-2 ARM instruction summary
Operation
Move
Arithmetic
Move
Move NOT
Move SPSR to register
Move CPSR to register
Move register to SPSR
Move register to CPSR
Move immediate to SPSR flags
Move immediate to CPSR flags
Add
Add with carry
Subtract
Subtract with carry
Subtract reverse subtract
Subtract reverse subtract with carry
Multiply
Multiply accumulate
Multiply unsigned long
Assembly syntax
MOV{cond}{S} Rd, <Oprnd2>
MVN{cond}{S} Rd, <Oprnd2>
MRS{cond} Rd, SPSR
MRS{cond} Rd, CPSR
MSR{cond} SPSR{field}, Rm
MSR{cond} CPSR{field}, Rm
MSR{cond} SPSR_f, #32bit_Imm
MSR{cond} CPSR_f, #32bit_Imm
ADD{cond}{S} Rd, Rn, <Oprnd2>
ADC{cond}{S} Rd, Rn, <Oprnd2>
SUB{cond}{S} Rd, Rn, <Oprnd2>
SBC{cond}{S} Rd, Rn, <Oprnd2>
RSB{cond}{S} Rd, Rn, <Oprnd2>
RSC{cond}{S} Rd, Rn, <Oprnd2>
MUL{cond}{S} Rd, Rm, Rs
MLA{cond}{S} Rd, Rm, Rs, Rn
UMULL{cond}{S} RdLo, RdHi, Rm, Rs
1-12
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ARM DDI 0029G