ARM7TDMI View Datasheet(PDF) - Unspecified

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ARM7TDMI

General-Purpose 32-Bit Microprocessors

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ARM7TDMI Technical Reference Manual

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Key to timing diagram conventions ............................................................................. xx

Instruction pipeline .................................................................................................... 1-3

ARM7TDMI processor block diagram ....................................................................... 1-7

Main processor .......................................................................................................... 1-8

ARM7TDMI processor functional diagram ................................................................ 1-9

ARM instruction set formats .................................................................................... 1-11

Thumb instruction set formats ................................................................................. 1-20

LIttle-endian addresses of bytes and halfwords within words ................................... 2-4

Big-endian addresses of bytes and halfwords within words ...................................... 2-5

Register organization in ARM state ........................................................................... 2-9

Register organization in Thumb state ..................................................................... 2-10

Mapping of Thumb-state registers onto ARM-state registers .................................. 2-11

Program status register format ................................................................................ 2-13

Simple memory cycle ................................................................................................ 3-4

Nonsequential memory cycle .................................................................................... 3-6

Sequential access cycles .......................................................................................... 3-7

Internal cycles ........................................................................................................... 3-8

Merged IS cycle ........................................................................................................ 3-9

Coprocessor register transfer cycles ....................................................................... 3-10

Memory cycle timing ............................................................................................... 3-10

Pipelined addresses ................................................................................................ 3-14

Depipelined addresses ............................................................................................ 3-15

SRAM compatible address timing ........................................................................... 3-16

ARM DDI 0029G

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