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A2V64S40 View Datasheet(PDF) - Unspecified

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A2V64S40CTP
64M Single Data Rate Synchronous DRAM
Pin Descriptions
SYMBOL
TYPE
DESCRIPTION
CLK
CKE
Input
Input
Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive
edge of CLK. CLK also increments the internal burst counter and controls the output registers.
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the
clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle),
ACTIVE POWER-DOWN (row active in any bank), DEEP POWER DOWN (all banks idle), or
CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous except after the
device enters power-down and self refresh modes, where CKE becomes asynchronous until
after exiting the same mode. The input buffers, including CLK, are disabled during power-down
and self refresh modes, providing low standby power. CKE may be tied HIGH.
Chip Select: /CS enables (registered LOW) and disables (registered HIGH) the command
decoder. All commands are masked when /CS is registered HIGH. /CS provides for external
/CS
Input
bank selection on systems with multiple banks. /CS is considered part of the command code.
/CAS,
/RAS,
/WE
LDQM,
UDQM,
Input
Input
Command Inputs: /CAS, /RAS, and /WE (along with /CS) define the command being entered.
Input/Output Mask: DQM is sampled HIGH and is an input mask signal for write accesses and an
output enable signal for read accesses. Input data is masked during a WRITE cycle. The output
buffers are placed in a High-Z state (two-clock latency) when during a READ cycle. LDQM
corresponds to DQ0–DQ7, UDQM corresponds to DQ8–DQ15. LDQM and UDQM are
considered same state when referenced www.DataSheet.co.kr as DQM.
BA0, BA1
Input
Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE, READ, WRITE or
PRECHARGE command is being applied. These pins also select between the mode register and
the extended mode register.
A0–A11
Input
Address Inputs: A0–A11 are sampled during the ACTIVE command (row address A0–A11) and
READ/WRITE command (column-address A0–A7; with A10 defining auto precharge) to select
one location out of the memory array in the respective bank. A10 is sampled during a
PRECHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank
selected by BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD
MODE REGISTER command.
DQ0–DQ15
NC
VDDQ
VSSQ
VDD
VSS
I/O
Supply
Supply
Supply
Supply
Data Input/Output: Data bus.
Internally Not Connected: These could be left unconnected, but it is recommended they be
connected or VSS.
DQ Power: Provide isolated power to DQs for improved noise immunity.
DQ Ground: Provide isolated ground to DQs for improved noise immunity.
Core Power Supply.
Ground.
Revision 2.1
Page 3/36
Sep., 2008
Datasheet pdf - http://www.DataSheet4U.net/
 

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