ST7263Bxx
Reset and clock management
Figure 12. Low voltage detector functional diagram
VDD
LOW VOLTAGE
DETECTOR
FROM
WATCHDOG
RESET
RESET
INTERNAL
RESET
Figure 13. Low Voltage Reset signal output
VIT+
VIT-
VDD
RESET
1. Hysteresis (VIT+-VIT-) = Vhys
Figure 14. Temporization timing diagram after an internal Reset
VDD
VIT+
Addresses
Temporization (4096 CPU clock cycles)
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Doc ID 7516 Rev 8
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