ST7263BD6 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

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ST7263BD6

Low speed USB 8-bit MCU family with up to 32 KB Flash/ROM, DFU capability, 8-bit ADC, WDG, timer, SCI and I²C

STMicroelectronics 

ST7263Bxx

Central processing unit

Condition Code register (CC)

Reset value: 111x1xxx

7

6

5

4

3

2

1

0

1

1

1

H

I

N

Z

C

Read/write

The 8-bit Condition Code register contains the interrupt mask and four flags representative

of the result of the instruction just executed. This register can also be handled by the PUSH

and POP instructions.

These bits can be individually tested and/or controlled by specific instructions.

Bit 4 H Half carry

This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU

during an ADD or ADC instruction. It is reset by hardware during the same

instructions.

0: No half carry has occurred.

1: A half carry has occurred.

This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD

arithmetic subroutines.

Bit 3 I Interrupt mask

This bit is set by hardware when entering in interrupt or by software to disable all

interrupts except the TRAP software interrupt. This bit is cleared by software.

0: Interrupts are enabled.

1: Interrupts are disabled.

This bit is controlled by the RIM, SIM and IRET instructions and is tested by the

JRM and JRNM instructions.

Note: Interrupts requested while I is set are latched and can be processed when I

is cleared. By default an interrupt routine is not interruptible because the I bit

is set by hardware at the start of the routine and reset by the IRET

instruction at the end of the routine. If the I bit is cleared by software in the

interrupt routine, pending interrupts are serviced regardless of the priority

level of the current interrupt routine.

Doc ID 7516 Rev 8

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