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AR0141CS View Datasheet(PDF) - ON Semiconductor

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AR0141CS
ON-Semiconductor
ON Semiconductor ON-Semiconductor
AR0141CS Datasheet PDF : 48 Pages
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AR0141CS
Table 3. BALL DESCRIPTIONS, 9 X 9 MM, 63BALL iBGA
Name
iBGA Pin
Type
Description
VAA
EXTCLK
B7, B8
C1
Power
Input
Analog power
External input clock
VDD_SLVS
C2
Power 0.3 V 0.6 V or 1.7 V 1.9 V port to HiSPi Output Driver. Set the
High_VCM (R0x306E[9]) bit to 1 when configuring VDD_SLVS to
1.7 V 1.9 V
SLVS3_N
C3
Output HiSPi serial data, lane 3, differential N
SLVS3_P
C4
Output HiSPi serial data, lane 3, differential P
DGND
C5, D4, D5, E5, F5, G5, H5 Power Digital ground
VDD
A6, A7, B6, C6, D6
Power Digital power
AGND
C7, C8
Power Analog ground
SADDR
D1
Input
TwoWire Serial address select. 0: 0x20, 1: 0x30
SCLK
D2
Input
TwoWire Serial clock input
SDATA
D3
I/O
TwoWire Serial data I/O
VAA_PIX
D7, D8
Power Pixel power
LINE_VALID
FRAME_VALID
PIXCLK
VDD_IO
DOUT8
DOUT9
DOUT10
DOUT11
TEST
DOUT4
DOUT5
DOUT6
DOUT7
TRIGGER
E1
E2
E3
E6, F6, G6, H6, H7
F1
F2
F3
F4
F7
G1
G2
G3
G4
G7
Output
Output
Output
Power
Output
Output
Output
Output
Input.
Output
Output
Output
Output
Input
Asserted when DOUT line data is valid
Asserted when DOUT frame data is valid
Pixel clock out. DOUT is valid on rising edge of this clock
I/O supply power
Parallel pixel data output
Parallel pixel data output
Parallel pixel data output
Parallel pixel data output (MSB)
Manufacturing test enable pin (connect to DGND)
Parallel pixel data output
Parallel pixel data output
Parallel pixel data output
Parallel pixel data output
Exposure synchronization input
OE_BAR
G8
Input
Output enable (active LOW)
DOUT0
H1
Output Parallel pixel data output (LSB)
DOUT1
H2
Output Parallel pixel data output
DOUT2
H3
Output Parallel pixel data output
DOUT3
H4
Output Parallel pixel data output
RESET_BAR
H8
Input
Asynchronous reset (active LOW). All settings are restored to factory
default
NC
E8
No connection
FLASH
E4
Output Flash control output
NC
E7
No connection
Reserved
F8
Reserved
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