AR0141CS
Previous Reg Address, N
N+1
N+2
S Slave Address 1 A Read Data
A Read Data A Read Data A
N+L−1
N+L
Read Data
AP
Figure 37. Sequential READ, Start from Current Location
Single WRITE to Random Location
This sequence (Figure 38) begins with the master
generating a start condition. The slave address/data
direction byte signals a WRITE and is followed by the HIGH
then LOW bytes of the register address that is to be written.
The master follows this with the byte of write data. The
WRITE is terminated by the master generating a stop
condition.
Previous Reg Address, N
Reg Address, M
M+1
S Slave Address 0 A Reg Address[15:8] A Reg Address[7:0] A
Write Data
AP
A
Figure 38. Single WRITE to Random Location
Sequential WRITE, Start at Random Location
This sequence (Figure 39) starts in the same way as the
single WRITE to random location (Figure 38). Instead of
generating a no−acknowledge bit after the first byte of data
has been transferred, the master generates an acknowledge
bit and continues to perform byte WRITEs until “L” bytes
have been written. The WRITE is terminated by the master
generating a stop condition.
Previous Reg Address, N
Reg Address, M
M+1
S Slave Address 0 A Reg Address[15:8] A Reg Address[7:0] A
Write Data
A
M+1
Write Data
M+2
M+3
M+L−2
A
Write Data
A
Write Data
A
Figure 39. Sequential WRITE, Start at Random Location
M+L−1
Write Data
M+L
A
A
P
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