AR0141CS View Datasheet(PDF) - ON Semiconductor

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AR0141CS

1/4‐inch Digital Image Sensor

ON Semiconductor 

AR0141CS

SLAVE MODE

The slave mode feature of the AR0141CS supports

triggering the start of a frame readout from a VD signal that

is supplied from an external device. The slave mode signal

allows for precise control of frame rate and register change

updates. The VD signal is an edge triggered input to the

trigger pin and must be at least 3 PIXCLK cycles wide.

Frame Valid VD Signal

Start of frame N

OB Rows (2, 4, or 8 rows)

Embedded Data Row (2 rows)

Active Data Rows

Blank Rows (2 rows)

Extra Vertical Blanking

(frame_length_lines − min_frame_length_lines)

Extra Delay (clocks)

Slave Mode Active State

End of frame N

Start of frame N + 1

The period between the

rising edge of the VD signal

and the slave mode ready

state is TFRAME + 16 clock

Figure 26. Slave Mode Active State and Vertical Blanking

If the slave mode is disabled, the new frame will begin

after the extra delay period is finished.

The slave mode will react to the rising edge of the input

VD signal if it is in an active state. When the VD signal is

received, the sensor will begin the frame readout and the

slave mode will remain inactive for the period of one frame

time plus 16 clock periods (TFRAME + (16 / CLK_PIX)).

After this period, the slave mode will re−enter the active

state and will respond to the VD signal.

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