Serial PLL Configuration
EXTCLK
(6−50 MHz)
pre_pll_clk_div
2 (1−64)
AR0141CS
FVC0
pll_multiplier
58 (32−384)
Vt_sys_clk_div
1 (1, 2, 4, 6, 8,
10,11, 12,14, 16)
Vt_pix_clk_div
6 (4−16)
CLK_PIX
FVC0
op_sys_clk_div
(default = 1)
op_pix_clk_div
12 (8,10, 12)
CLK_OP
FSERIAL
1/2
FSERIAL_CLK
Figure 20. PLL for the Serial Interface
The sensor will use op_sys_clk_div and op_pix_clk_div
to configure the output clock per lane (CLK_OP). The
configuration will depend on the number of active lanes (1,
2, or 4) configured. To configure the sensor protocol and
number of lanes, refer to “Serial Configuration”.
Table 8. PLL PARAMETERS FOR THE SERIAL INTERFACE
Parameter
Symbol
Min
External Clock
VCO Clock
Readout Clock
Output Serial Data Rate Per Lane
Output Serial Clock Speed Per Lane
EXTCLK
FVCO
CLK_PIX
FSERIAL
FSERIAL_CLK
6
384
300 (HiSPi)
150 (HiSPi)
Max
50
768
74.25
600 (HiSPi)
350(HiSPi)
Unit
MHz
MHz
Mpixel/s
Mbps
MHz
Configure the serial output so that it adheres to the
following rules:
• The maximum data−rate per lane (FSERIAL) is
600Mbps/lane (HiSPi)
• Configure the output pixel rate per lane (CLK_OP) so
that the sensor output pixel rate matches the peak pixel
rate (2 × CLK_PIX)
⎯ 4−lane: 4 x CLK_OP = 2 × CLK_PIX = Pixel Rate
(max: 148.5 Mpixel/s)
⎯ 2−lane: 2 x CLK_OP = 2 × CLK_PIX = Pixel Rate
(max: 74.25 Mpixel/s)
Table 9. EXAMPLE PLL CONFIGURATIONS FOR THE SERIAL INTERFACE
4−lane
2−lane
Parameter
FVCO
vt_sys_clk_div
vt_pix_clk_div
op_sys_clk_div
op_pix_clk_div
FSERIAL
FSERIAL_CLK
12−bit
445.5
1
6
1
12
445.5
222.75
12−bit
445.5
1
12
1
12
445.5
222.75
Units
MHz
MHz
MHz
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