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AR0141CS2C00SUEA0-DP View Datasheet(PDF) - ON Semiconductor

Part Name
Description
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AR0141CS2C00SUEA0-DP
ON-Semiconductor
ON Semiconductor ON-Semiconductor
AR0141CS2C00SUEA0-DP Datasheet PDF : 48 Pages
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SENSOR PLL
VCO
AR0141CS
EXTCLK
(650 MHz)
pre_pll_clk_div
2(164)
pll_multiplier
58(32384)
FVC0
Figure 18. PLL Dividers Affecting VCO Frequency
The sensor contains a phaselocked loop (PLL) that is
used for timing generation and control. The required VCO
clock frequency is attained through the use of a prePLL
clock divider followed by a multiplier. The PLL multiplier
should be an even integer. If an odd integer (M) is
programmed, the PLL will default to the lower (M1) value
to maintain an even multiplier value. The multiplier is
followed by a set of dividers used to generate the output
clocks required for the sensor array, the pixel analog and
digital readout paths, and the output parallel and serial
interfaces.
Parallel PLL Configuration
FVC0
EXTCLK
(650 MHz)
pre_pll_clk_div
2(164)
pll_multiplier
58(32384)
vt_sys_clk_div
1 (1,2,4,6,8,10
12,14,16)
vt_pix_clk_div
6(416)
CLK_OP
(Max 74.25 Mp/s)
Figure 19. PLL for the Parallel Interface
The maximum output of the parallel interface is 74.25
MPixel/s. The sensor will not use the FSERIAL,
FSERIAL_CLK, or CLK_OP when configured to use the
parallel interface.
Table 6. PLL PARAMETERS FOR THE PARALLEL INTERFACE
Parameter
Symbol
Min
External Clock
EXTCLK
6
VCO Clock
FVCO
384
Output Clock
CLK_OP
Max
50
768
74.25
Unit
MHz
MHz
Mpixel/s
Table 7. EXAMPLE PLL CONFIGURATION FOR THE PARALLEL INTERFACE
Parameter
Value
FVCO
vt_sys_clk_div
1
vt_pix_clk_div
6
CLK_OP
Output pixel rate
Output
445.5 MHz (Max)
74.25 MPixel/s (= 445.5 MHz / 6)
74.25 MPixel/s
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