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AR0141CS(2015) View Datasheet(PDF) - ON Semiconductor

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AR0141CS
(Rev.:2015)
ON-Semiconductor
ON Semiconductor ON-Semiconductor
AR0141CS Datasheet PDF : 63 Pages
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AR0141CS: 1/4-Inch Digital Image Sensor
Two-Wire Serial Register Interface
Sequential READ, Start from Random Location
This sequence (Figure 35) starts in the same way as the single READ from random loca-
tion (Figure 33). Instead of generating a no-acknowledge bit after the first byte of data
has been transferred, the master generates an acknowledge bit and continues to
perform byte READs until “L” bytes have been read.
Figure 35: Sequential READ, Start from Random Location
Previous Reg Address, N
Reg Address, M
M+1
S Slave Address 0 A Reg Address[15:8] A Reg Address[7:0] A Sr Slave Address 1 A
Read Data A
M+1
Read Data A
M+2
M+3
Read Data A
M+L-2
Read Data A
M+L-1
M+L
Read Data A P
Sequential READ, Start from Current Location
This sequence (Figure 36) starts in the same way as the single READ from current loca-
tion (Figure 34). Instead of generating a no-acknowledge bit after the first byte of data
has been transferred, the master generates an acknowledge bit and continues to
perform byte READs until “L” bytes have been read.
Figure 36: Sequential READ, Start from Current Location
Previous Reg Address, N
N+1
N+2
S Slave Address 1 A
Read Data A
Read Data A
Read Data A
N+L-1
N+L
Read Data A P
Single WRITE to Random Location
This sequence (Figure 37) begins with the master generating a start condition. The slave
address/data direction byte signals a WRITE and is followed by the HIGH then LOW
bytes of the register address that is to be written. The master follows this with the byte of
write data. The WRITE is terminated by the master generating a stop condition.
Figure 37: Single WRITE to Random Location
Previous Reg Address, N
Reg Address, M M+1
S Slave Address 0 A Reg Address[15:8] A Reg Address[7:0] A
Write Data
AP
A
AR0141CS DS Rev. D Pub. 6/15 EN
44
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