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MRF175LU View Datasheet(PDF) - Motorola => Freescale

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Description
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MRF175LU Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
INPUT AND OUTPUT IMPEDANCE
175 225 300
f = 400 MHz
150
100
175 225 300 f = 400 MHz
Zin
150
100
ZOL*
30
30
Zo = 10
VDD = 28 V, IDQ = 100 mA,
(Pout = 100 W)
f
Zin
MHz
Ohms
ZOL*
Ohms
30 2.80 – j4.00 3.65 – j1.30
100 1.40 – j2.80 2.60 – j1.50
150 1.10 – j1.90 2.10 – j1.40
175 1.00 – j1.25 1.80 – j1.20
225 0.95 – j0.65 1.50 – j0.80
300 0.95 + j0.20 1.35 – j0.30
400 1.05 + j1.15 1.45 + j0.55
ZOL* = CONJUGATE OF THE OPTIMUM
LOAD IMPEDANCE INTO WHICH THE
DEVICE OUTPUT OPERATES AT A GIVEN
OUTPUT POWER, VOLTAGE AND FREQUENCY.
RF POWER MOSFET CONSIDERATIONS
MOSFET CAPACITANCES
The physical structure of a MOSFET results in capacitors
between the terminals. The metal oxide gate structure deter-
mines the capacitors from gate–to–drain (Cgd), and gate–to–
source (Cgs). The PN junction formed during the fabrication
of the FET results in a junction capacitance from drain–to–
source (Cds).
These capacitances are characterized as input (Ciss), out-
put (Coss) and reverse transfer (Crss) capacitances on data
sheets. The relationships between the inter–terminal capaci-
tances and those given on data sheets are shown below. The
Ciss can be specified in two ways:
1. Drain shorted to source and positive voltage at the gate.
2. Positive voltage of the drain in respect to source and zero
volts at the gate. In the latter case the numbers are lower.
However, neither method represents the actual operat-
ing conditions in RF applications.
Cgd
GATE
Cgs
DRAIN
Cds
SOURCE
Ciss = Cgd + Cgs
Coss = Cgd + Cds
Crss = Cgd
LINEARITY AND GAIN CHARACTERISTICS
In addition to the typical IMD and power gain data pres-
ented, Figure 3 may give the designer additional information
on the capabilities of this device. The graph represents the
small signal unity current gain frequency at a given drain cur-
rent level. This is equivalent to fT for bipolar transistors.
Since this test is performed at a fast sweep speed, heating of
the device does not occur. Thus, in normal use, the higher
temperatures may degrade these characteristics to some ex-
tent.
DRAIN CHARACTERISTICS
One figure of merit for a FET is its static resistance in the
full–on condition. This on–resistance, VDS(on), occurs in the
linear region of the output characteristic and is specified un-
der specific test conditions for gate–source voltage and drain
current. For MOSFETs, VDS(on) has a positive temperature
coefficient and constitutes an important design consideration
at high temperatures, because it contributes to the power
dissipation within the device.
GATE CHARACTERISTICS
The gate of the FET is a polysilicon material, and is electri-
cally isolated from the source by a layer of oxide. The input
resistance is very high — on the order of 109 ohms — result-
ing in a leakage current of a few nanoamperes.
Gate control is achieved by applying a positive voltage
slightly in excess of the gate–to–source threshold voltage,
VGS(th).
Gate Voltage Rating — Never exceed the gate voltage
rating. Exceeding the rated VGS can result in permanent
damage to the oxide layer in the gate region.
Gate Termination — The gates of these devices are
essentially capacitors. Circuits that leave the gate open–cir-
cuited or floating should be avoided. These conditions can
result in turn–on of the devices due to voltage build–up on
the input capacitor due to leakage currents or pickup.
MRF175LU MRF175LV
6
MOTOROLA RF DEVICE DATA
 

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