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DAC5687 View Datasheet(PDF) - Texas Instruments

Part NameDescriptionManufacturer
DAC5687 16-BIT, 500 MSPS 2?8 INTERPOLATING DUAL-CHANNEL DIGITAL-TO-ANALOG CONVERTER (DAC) Texas-Instruments
Texas Instruments Texas-Instruments
DAC5687 Datasheet PDF : 80 Pages
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DAC5687
SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006
PHSTR
Only Must Be High for One clk_in Period
clk_in
Input Delay Line + FIFO Delay
www.ti.com
clk_out
phstr at FIFO
Output
clk_cmix
Sequencer
Reset
Sequencer
fs/2
Sequencer
fs/4
0 180 0 180
Figure 57. CMIX Reset Synchronization Timing
0 90 180 270 0 90
T0155-01
In addition to the reset function provided by the PHSTR signal, the phstr_del(1:0) bits in register ATEST allow
the user to select the initial (reset) state. Changing the cm_mode lower 2 bits produces the same phase shift
results.
Fix Mix Selection
fS/2
fS/2
fS/4
fS/4
fS/4
fS/4
Table 14. Initial State of CMIX After Reset
phstr_del(1:0)
00 and 10
01 and 11
00
01
10
11
Initial State at PHSTR
Normal
180-degree shift
Normal
90-degree shift
180-degree shift
270-degree shift
Input Clock Synchronization of Multiple DAC5687s
For applications where multiple DAC5687 chips are used, clock synchronization is best achieved by using
dual-clock mode with the FIFO disabled or the PLL-clock mode. In the dual-clock mode with FIFO disabled, an
appropriate clock PLL such as the CDC7005 is required to provide the DAC and input rate clocks that meet the
skew requirement talign (see Figure 47). An example for synchronizing multiple DAC5687 devices in dual clock
mode with two CDC7005s is shown in Figure 58. When using the internal PLL-clock mode, synchronization of
multiple using PHSTR is completely deterministic due to the phase/frequency detector in the PLL feedback loop.
All chips using the same CLK1/CLK1C input clock have identical internal clocking phases.
50
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