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DAC5687 View Datasheet(PDF) - Texas Instruments

Part NameDescriptionManufacturer
DAC5687 16-BIT, 500 MSPS 2?8 INTERPOLATING DUAL-CHANNEL DIGITAL-TO-ANALOG CONVERTER (DAC) Texas-Instruments
Texas Instruments Texas-Instruments
DAC5687 Datasheet PDF : 80 Pages
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www.ti.com
DAC5687
SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006
qmc_gain_a/210
{0, 1/210, ..., 2 – 1/210}
11
I(t)
X
Σ
10
X
Q(t)
qmc_phase/210
X
{–1/2, –1/2 + 1/210, ..., 1/2 – 1/210}
11
qmc_gain_b/210
{0, 1/210, ..., 2 – 1/210}
Figure 40. QMC Block Diagram
B0164−01
L-
O
side-
band
L-
O
side-
band
Uncorrected
Corrected
C003
Figure 41. Example of Sideband Optimization Using QMC Phase and Gain Adjustments
DAC Offset Control
Registers daca_offset and dacb_offset control the I and Q path offsets and are 13-bit values with a range of
–4096 to 4095. The DAC offset value adds a digital offset to the digital data before digital-to-analog conversion.
The qmc_gain_a and qmc_gain_b registers can be used to back off the signal before the offset to prevent
saturation when the offset value is added to the digital signal. The offset values are in 2s-complement format.
It takes four DAC clock cycles to update the 14-bit DAC5687 offset registers. During the first clock cycle, the two
MSBs, daca_offset(13:12) and dacb_offset(13:12), are updated, followed by daca_offset(11:8) and
dacb_offset(11:8) on the second clock cycle, daca_offset(7:4) and dacb_offset(7:4) on the third clock cycle, and
daca_offset(3:0) and dacb_offset(3:0) on the fourth clock cycle.
Copyright © 2005–2006, Texas Instruments Incorporated
Product Folder Link(s): DAC5687
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