SLWS164E â€“ FEBRUARY 2005 â€“ REVISED SEPTEMBER 2006
Synchronization of the NCO occurs by resetting the NCO accumulator to zero with assertion of PHSTR. See the
following NCO Synchronization section. Frequency word freq in the frequency register is added to the
accumulator every clock cycle. The output frequency of the NCO is
freq v 231
(freq * 232)
freq u 231
where fNCO_CLK is the clock frequency of the NCO circuit. In X4 mode, the NCO clock frequency is the same as
the DAC sample rate, fDAC. The maximum clock frequency the NCO can operate at is 320 MHz â€“ in X4 FMIX
mode, where FMIX operates at the DAC update rate, the DAC updated rate is limited to 320 MSPS. In X2, X4L
and X8 modes, the NCO circuit is followed by a further 2Ã— interpolation and so fNCO_CLK = fDAC/2 and operates at
fDAC = 500 MHz.
Treating channels A and B as a complex vector I + I Ã— Q where I(t) = A(t) and Q(t) = B(t), the output of FMIX
IOUT(t) and QOUT(t) is
IOUT(t) = (IIN(t)cos(2Ï€fNCOt + Î´) â€“ QIN(t)sin(2Ï€fNCOt + Î´)) Ã— 2(NCO_GAIN â€“ 1)
QOUT(t) = (IIN(t)sin(2Ï€fNCOt + Î´) + QIN(t)cos(2Ï€fNCOt + Î´)) Ã— 2(NCO_GAIN â€“ 1)
where t is the time since the last resetting of the NCO accumulator, Î´ is the initial accumulator value, and
NCO_GAIN, bit 6 in register CONFIG2, is either 0 or 1. Î´ is given by
Î´ = 2Ï€ Ã— phase(15:0)/216.
The maximum output amplitude of FMIX occurs if IIN(t) and QIN(t) are simultaneously full-scale amplitude and the
sine and cosine arguments 2Ï€fNCOt + Î´ = (2N â€“ 1) Ã— Ï€/4 (N = 1, 2, ...). With NCO_GAIN = 0, the gain through
FMIX is sqrt(2)/2 or â€“3 dB. This loss in signal power is in most cases undesirable, and it is recommended that
the gain function of the QMC block be used to increase the signal by 3 dB to 0 dBFS by setting qmca_gain and
qmcb_gain each to 1446 (decimal).
With NCO_GAIN = 1, the gain through FMIX is sqrt(2) or 3 dB, which can cause clipping of the signal if IIN(t) and
QIN(t) are simultaneously near full-scale amplitude, and should therefore be used with caution.
Coarse Mixer (CMIX)
The coarse mixer block provides mixing capability at the DAC output rate with fixed frequencies of fS/2 or fS/4.
The coarse mixer output phase sequence is selected by the cm_mode(3:0) bits in register CONFIG2 and is
shown in Table 10.
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