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BQ24157S View Datasheet(PDF) - Texas Instruments

Part NameDescriptionManufacturer
BQ24157S 1.55-A Fully Integrated Switch-Mode One-Cell Li-Ion Charger With Full USB Compliance and USB-OTG Support TI
Texas Instruments TI
BQ24157S Datasheet PDF : 45 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Not Recommended for New Designs
bq24157S
SLUSB76B – FEBRUARY 2013 – REVISED MAY 2015
www.ti.com
Electrical Characteristics (continued)
Circuit of Figure 28, VBUS = 5 V, HZ_MODE = 0, OPA_MODE = 0 (CD = 0), TJ = –40°C to 125°C, TJ = 25°C for typical
values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
INPUT CURRENT LIMITING
IIN_LIMIT
Input current limiting threshold
VREF BIAS REGULATOR
IIN = 100 mA
IIN = 500 mA
TJ = 0°C to 125°C
TJ = –40°C to 125°C
TJ = 0°C to 125°C
TJ = –40°C to 125°C
88
93
98
mA
86
93
98
450
475
500
mA
440
475
500
VREF
Internal bias regulator voltage
VREF output short current limit
BATTERY RECHARGE THRESHOLD
VBUS > VIN(min) or V(CSOUT) > VBUS(min),
I(VREF) = 1 mA, C(VREF) = 1 μF
2
6.5
V
30
mA
V(RCH)
Recharge threshold voltage
Deglitch time
STAT OUTPUTS
Below V(OREG)
V(SCOUT) decreasing below threshold,
tFALL = 100 ns, 10-mV overdrive
100
120
150 mV
130
ms
VOL(STAT)
Low-level output saturation voltage, STAT pin
High-level leakage current for STAT
IO = 10 mA, sink current
Voltage on STAT pin is 5 V
0.55
V
1 μA
I2C BUS LOGIC LEVELS AND TIMING CHARACTERISTICS
VOL
Output low threshold level
VIL
Input low threshold level
VIH
Input high threshold level
I(BIAS)
Input bias current
f(SCL)
SCL clock frequency
BATTERY DETECTION
IO = 10 mA, sink current
V(pullup) = 1.8 V, SDA and SCL
V(pullup) = 1.8 V, SDA and SCL
V(pullup) = 1.8 V, SDA and SCL
0.4
V
0.4
V
1.2
V
1 μA
3.4 MHz
I(DETECT)
Battery detection current before charge done
(sink current) (2)
tDETECT
Battery detection time
SLEEP COMPARATOR
Begins after termination detected,
V(CSOUT) V(OREG)
–0.5
mA
262
ms
V(SLP)
Sleep-mode entry threshold,
VBUS – VCSOUT
V(SLP_EXIT)
Sleep-mode exit hysteresis
Deglitch time for VBUS rising above V(SLP) +
V(SLP_EXIT)
UNDERVOLTAGE LOCKOUT (UVLO)
2.3 V V(CSOUT) V(OREG), VBUS falling
2.3 V V(CSOUT) V(OREG)
Rising voltage, 2-mV overdrive, tRISE = 100 ns
0
40
100 mV
140
200
260 mV
30
ms
UVLO
UVLO(HYS)
IC active threshold voltage
IC active hysteresis
Power up delay
VBUS rising – exits UVLO
VBUS falling below UVLO – enters UVLO
3.05
3.3 3.55
V
120
150
mV
140
ms
PWM
Voltage from BOOT pin to SW pin
During charge or boost operation
6.5
V
Internal top reverse blocking MOSFET on-
resistance
IIN(LIMIT) = 500 mA, measured from VBUS to PMID
180
250
Internal top N-channel switching MOSFET on-
resistance
Internal bottom N-channel MOSFET on-
resistance
Measured from PMID to SW,
VBOOT – VSW= 4 V
Measured from SW to PGND
120
250 m
110
210
f(OSC)
Oscillator frequency
Frequency accuracy
–10%
3.0
MHz
10%
D(MAX)
Maximum duty cycle
99.5%
D(MIN)
Minimum duty cycle
0
Synchronous mode to non-synchronous mode
transition current threshold(2)
Low-side MOSFET cycle-by-cycle current sensing
100
mA
(2) Bottom N-channel FET always turns on for approximately 30 ns, and then turns off if current is too low.
6
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