TE28F256J3D-95 View Datasheet(PDF) - Intel
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TE28F256J3D-95 Datasheet PDF : 66 Pages
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Intel® Embedded Flash Memory (J3 v. D)
Revision History
Date
February 2007
March 2007
May 2007
August 2007
November 2007
December 2007
Revision Description
001 Initial release
Revised the following graphics to support 256Mbit:
• Figure 1, “Intel® Embedded Flash Memory (J3 v. D) Memory Block Diagram (32, 64 and
128, 256Mbit)” on page 10.
002
• Figure 5, “Easy BGA Ballout (32/64/128/256 Mbit)” on page 15.
• Figure 28, “Decoder for Discrete Family, 32-, 64-, 128-, 256-Mbit (monolithic)” on
page 67.
003 Minor revisions
004 Updated title page to reflect a 256-Mbit monolithic die.
005 Updated the 65nm pre-enabling information
006 Revised the Signal Description Table and clarified Chip Enable (CE) definitions
December 2007
Document Number: 316577-006
Datasheet
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