TE28F256J3D-95 View Datasheet(PDF) - Intel

Part Name

Description

View to exact match

TE28F256J3D-95

Intel® Embedded Flash Memory (J3 v. D)

Intel 

Intel® Embedded Flash Memory (J3 v. D)

8.3

8.3.1

8.4

The CUI does not occupy an addressable memory location. It is written when the device

is enabled and WE# is active. The address and data needed to execute a command are

latched on the rising edge of WE# or the first edge of CE0, CE1, or CE2 that disables

the device (see Table 16 on page 31). Standard microprocessor write timings are used.

Standby

CE0, CE1, and CE2 can disable the device (see Table 16 on page 31) and place it in

standby mode. This manipulation of CEx substantially reduces device power

consumption. D[15:0] outputs are placed in a high-impedance state independent of

OE#. If deselected during block erase, program, or lock-bit configuration, the WSM

continues functioning, and consuming active power until the operation completes.

Reset/Power-Down

RP# at VIL initiates the reset/power-down mode.

In read modes, RP#-low deselects the memory, places output drivers in a high-

impedance state, and turns off numerous internal circuits. RP# must be held low for a

minimum of tPLPH. Time tPHQV is required after return from reset mode until initial

memory access outputs are valid. After this wake-up interval, normal operation is

restored. The CUI is reset to read array mode and Status Register is set to 0080h.

During Block Erase, Program, or Lock-Bit Configuration modes, RP#-low will abort the

operation. In default mode, STS transitions low and remains low for a maximum time

of tPLPH + tPHRH until the reset operation is complete. Memory contents being altered

are no longer valid; the data may be partially corrupted after a program or partially

altered after an erase or lock-bit configuration. Time tPHWL is required after RP# goes to

logic-high (VIH) before another command can be written.

As with any automated device, it is important to assert RP# during system reset. When

the system comes out of reset, it expects to read from the flash memory. Automated

flash memories provide status information when accessed during Block Erase, Program,

or Lock-Bit Configuration modes. If a CPU reset occurs with no flash memory reset,

proper initialization may not occur because the flash memory may be providing status

information instead of array data. Intel® Flash memories allow proper initialization

following a system reset through the use of the RP# input. In this application, RP# is

controlled by the same RESET# signal that resets the system CPU.

Device Commands

When VPEN ≤ VPENLK, only read operations from the Status Register, CFI, identifier

codes, or blocks are enabled. Placing VPENH on VPEN additionally enables block erase,

program, and lock-bit configuration operations. Device operations are selected by

writing specific commands to the Command User Interface (CUI). The CUI does not

occupy an addressable memory location. It is the mechanism through which the flash

device is controlled.

A command sequence is issued in two consecutive write cycles - a Setup command

followed by a Confirm command. However, some commands are single-cycle

commands consisting of a setup command only. Generally, commands that alter the

contents of the flash device, such as Program or Erase, require at least two write cycles

to guard against inadvertent changes to the flash device. Flash commands fall into two

categories: Basic Commands and Extended Commands. Basic commands are

recognized by all Intel® Flash devices, and are used to perform common flash

operations such as selecting the read mode, programming the array, or erasing blocks.

Extended commands are product-dependant; they are used to perform additional

features such as software block locking. Table 19 describes all applicable commands on

Intel® Embedded Flash Memory (J3 v. D).

Datasheet

34

December 2007

Document Number: 316577-006

Share Link: