FM75 View Datasheet(PDF) - Fairchild Semiconductor

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FM75

Low-Voltage Two-Wire Digital Temperature Sensor with Thermal Alarm

Fairchild Semiconductor 

Basic Operation

The FM75 temperature sensing circuitry continuously

produces analog voltage proportional to the device tem-

perature. At regular intervals, the FM75 converts the

analog voltage to a two’s complement digital value,

which is placed into the temperature register.

The FM75 has an SMBus-compatible digital serial inter-

face that allows access to the data in the temperature

register at any time. In addition, the serial interface pro-

vides access to all other FM75 registers to customize

operation of the device.

The FM75 temperature-to-digital conversion can have 9,

10, 11, or 12-bit resolution selected, providing 0.5°C,

0.25°C, 0.125°C, and 0.0625°C temperature resolution,

respectively. At power-up, the default conversion resolu-

tion is 9-bits. The conversion resolution is controlled by

the R0 and R1 bits in the configuration register.

Table 1 gives examples of the relationship between the

output digital data and the external temperature. The

9-bit, 10-bit, 11-bit, and 12-bit columns in Table 1 indicate

the right-most bit in the output data stream that can con-

tain temperature information for each conversion accu-

racy. Since the output digital data is in two’s-complement

format, the most significant bit of the temperature is the

“sign” bit. If the sign bit is zero, the temperature is posi-

tive; if the sign bit is one, the temperature is negative.

The FM75 has a shutdown mode that reduces the oper-

ating current to 150nA. This mode is controlled by the

SD bit in the configuration register.

Power-Up Default Conditions

The FM75 powers up in the following default state:

• Thermostat mode: comparator mode

• OS polarity: active LOW

• Fault tolerance: 1 fault (i.e., F0 = 0 and F1 = 0 in the

configuration register)

• TOS: 80°C

• THYST: 75°C

• Register pointer: 00 (temperature register)

• Conversion resolution: 9 bits (i.e., R0 = 0 and R1 = 0

in the configuration register)

After power-up, these conditions can be reprogrammed

via the serial interface. Refer to the Serial Data Bus

Operation section for FM75 programming instructions.

Thermal Alarm Function

The FM75 thermal alarm function provides programma-

ble thermostat capability and allows the FM75 to function

as a stand-alone thermostat without using the serial

interface. The Over-Limit Signal (OS) output is the alarm

output. This signal is an open-drain output and, at

power-up, this pin is configured with active-low polarity.

Table 1. Relationship Between Temperature

and Digital Output

Temperature

Digital Output

Number of

Sig

bits used

by

conversion

bit

bit

bit

bit

Always

zero

resolution 9 10 11 12

12-Bit Resolution

0000

All

Temperatures

11-Bit Resolution

10 -Bit Resolution

0 0000

0 0 0000

9-Bit Resolution

0 0 0 0000

+125 C

0 111 1101 0 0 0 0 0000

+100.0625 C 0 110 0100 0 0 0 1 0000

+50.125 C

0 011 0010 0 0 1 0 0000

+12.25 C

0 000 1100 0 1 0 0 0000

0C

0 000 0000 0 0 0 0 0000

-20.5 C

1 110 1011 1 0 0 0 0000

-33.25C

1 101 1110 1 1 0 0 0000

-45.0625 C

1 101 0010 1 1 1 1 0000

-55C

1 100 1001 0 0 0 0 0000

The OS polarity is controlled by the POL bit in the config-

uration register. The programmable upper trip-point tem-

perature for the thermal alarm is stored in the TOS

register. The programmable hysteresis temperature (i.e.,

the lower trip point) is stored in the THYST register.

The thermal alarm has two modes of operation: compar-

ator mode and interrupt mode. At power-up, the default

is comparator mode. The alarm mode is controlled by the

CMP/INTR bit in the configuration register.

Fault Tolerance

For both comparator and Interrupt modes, the alarm

“fault tolerance” setting plays a role in determining when

the OS output is activated. Fault tolerance refers to the

number of consecutive times an error condition must be

detected before the user is notified. Higher fault toler-

ance settings can help eliminate false alarms caused by

noise in the system. The alarm fault tolerance is con-

trolled by bits F0 and F1 in the configuration register.

These bits can be used to set the fault tolerance to 1, 2,

4, or 6, as shown in Table 4. At power-up, these bits both

default to 0 (fault tolerance = 1).

© 2006 Fairchild Semiconductor Corporation

FM75 Rev. 1.0.8

6

www.fairchildsemi.com

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