TDA8133_94 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
View to exact match
TDA8133_94 Datasheet PDF : 5 Pages
| |||
TDA8133
ELECTRICAL CHRACTERISTICS (VIN1 = 7V, VIN2 = 10V, Tj = 25oC, unless otherwise specified)
Symbol
VO1
VO2
VO1
VO2
Output Voltage
Output Voltage
Output Voltage
Output Voltage
Parameter
VIO1,2 Dropout Voltage
VO1,2LI Line Regulation
VO1,2LO Load Regulation
IQ Quiescent Current
VO1RST Reset Thrseshold Voltage
Test Conditions
IO1 = 10mA
IO2 = 10mA
7V < VIN1 < 14V
10V < VIN2 < 14V
5mA < IO1,2 < 750mA
IO1,2 = 750mA
7V < VIN1 < 14V
10V < VIN2 < 14V
IO1,2 = 200mA
5mA < IO1 < 0.6A
5mA < IO2 < 0.6A
IO1 = 10mA
Output 2 Disabled
K = VO1
Min.
5
7.84
4.9
7.7
K - 0.4
VRTH Reset Thrseshold Hysteresis
See circuit description
tRD Reset Pulse Delay
Ce = 100nF
See circuit description
VRL Saturation Voltage in Reset Condition
I5 = 5mA
IRH
KO1,2
Leakage Current in Normal Condition at Pin 6
Output Voltage Thermal Drift
V5 = 10V
Tj = 0 to 125oC
KO
=
∆VO ⋅ 106
∆T ⋅ VO
IO1,2SC Short Circuit Output Current
VIN1 = 7V, VIN2 = 10V
VIN1,2 = 16V (see Note)
VDISH Disable Voltage High (out 2 active)
VDISL Disable Voltage Low (out 2 disabled)
IDIS Disable Bias Current
0V < VDIS < 7V
Tjsd Junction Temperature for Thermal Shut Down
Note : Safe permanent short-circuit is only guaranteed for input voltages up to 16V.
20
2
-100
Typ.
5.1
8
K-
0.25
50
25
100
145
Max. Unit
5.2
V
8.16
V
5.3
V
8.3
V
1.4
V
50
mV
80
mV
100 mV
160 mV
2
mA
K - 0.1 V
75
mV
ms
0.4
V
10
µA
ppm/oC
1.6
A
1
A
V
0.8
V
2
µA
oC
CIRCUIT DESCRIPTION
The TDA8133 is a dual voltage regulator with Reset
and Disable.
The two regulation parts are supplied from one
voltage reference circuit trimmed by zener zap
during EWS test.
Since the supply voltage of this last is connected at
Pin 1 (VIN1), the regulator 2 will not work if Pin 1 is
not supplied.
The outputs stage have been realized in darlington
configuration with a drop typical 1.2V.
The disable circuit, switch-off the output 2 if a
voltage lower than 0.8V is applied at Pin 4.
The Reset circuit checks the voltage at the out-
put 1. If this one goes below VOUT - 0.25V (4.85V
typ.), the comparator "a" (see Figure 1) discharges
rapidly the capacitor Ce and the reset output goes
at once Low. When the voltage at the out1 rises
above VOUT - 0.2V (4.9V typ.), the voltage VCe
increases linearly to 2.5V corresponding to a delay
td following the law :
t1 =
Ce ⋅ 2.5V
10µA
(see Figure 2),
then the reset output goes high again. To avoid
gliches in the reset output, the second comparator
"b" has a large hysteresis (1.9V).
3/5
|
|
Share Link: 