74LV175 View Datasheet(PDF) - Philips Electronics
Part Name
Description
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74LV175 Datasheet PDF : 13 Pages
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Philips Semiconductors
Quad D-type flip-flop with reset; positive-edge trigger
Product specification
74LV175
AC WAVEFORMS
VM = 1.5 V at VCC ≥ 2.7 V;
VM = 0.5 V × VCC at VCC < 2.7 V.
VOL and VOH are the typical output voltage drop that occur with the
output load.
VI
CP INPUT
GND
VOH
Qn OUTPUT
VOL
VOH
Qn OUTPUT
VOL
1/fmax
VM
tW
tPHL
VM
tPLH
VM
tPLH
tPHL
SV00604
Figure 1. Clock (CP) to outputs (Qn, Qn) propagation delays,
the clock pulse width and the maximum clock pulse frequency.
VI
MR INPUT
GND
VI
CP INPUT
GND
VOH
Qn OUTPUT
VOL
VOH
Qn OUTPUT
VOL
VM
tW
tPHL
VM
tPLH
VM
trem
VM
SV00605
Figure 2. Master reset (MR) pulse width,
the master reset to outputs (Qn, Qn) propagation delay
and master reset to clock (CP) removal time.
VI
CP INPUT
GND
VI
Dn INPUT
GND
VOH
Qn OUTPUT
VOL
VOH
Qn OUTPUT
VOL
VM
tsu
th
VM
VM
VM
tsu
th
The shaded areas indicate when the input is permitted to change for
predictable output performance.
SV00606
Figure 3. Data set-up and hold times for data input (Dn).
TEST CIRCUIT
VCC
PULSE
GENERATOR
VI
RT
D.U.T.
VO
50pF
CL
RL = 1k
Test Circuit for switching times
DEFINITIONS
RL = Load resistor
CL = Load capacitance includes jig and probe capacitance
RT = Termination resistance should be equal to ZOUT of pulse generators.
TEST
tPLH/tPHL
VCC
< 2.7V
2.7–3.6V
VI
VCC
2.7V
SV00901
Figure 4. Load circuitry for switching times.
1998 May 20
7
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