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FDS6898AZ_10 View Datasheet(PDF) - Fairchild Semiconductor

Part NameDescriptionManufacturer
FDS6898AZ_10 Dual N-Channel Logic Level PWM Optimized PowerTrench® MOSFET Fairchild
Fairchild Semiconductor Fairchild
FDS6898AZ_10 Datasheet PDF : 5 Pages
1 2 3 4 5
Electrical Characteristics
Symbol
Parameter
TA = 25°C unless otherwise noted
Test Conditions
Min Typ Max Units
Off Characteristics
BVDSS
Drain–Source Breakdown Voltage VGS = 0 V, ID = 250 µA
20
BVDSS Breakdown Voltage Temperature
ID = 250 µA, Referenced to 25°C
21
TJ
Coefficient
IDSS
Zero Gate Voltage Drain Current
VDS = 16 V, VGS = 0 V
V
mV/°C
1
µA
IGSSF
Gate–Body Leakage, Forward
VGS = 12 V, VDS = 0 V
10
µA
IGSSR
Gate–Body Leakage, Reverse
VGS = –12 V, VDS = 0 V
–10
µA
On Characteristics (Note 2)
VGS(th)
VGS(th)
TJ
RDS(on)
Gate Threshold Voltage
Gate Threshold Voltage
Temperature Coefficient
Static Drain–Source
On–Resistance
ID(on)
On–State Drain Current
gFS
Forward Transconductance
VDS = VGS,
ID = 250 µA
0.5
1
1.5
V
ID = 250 µA, Referenced to 25°C
–3.5
mV/°C
VGS = 4.5 V, ID = 9.4 A
VGS = 2.5 V, ID = 8.3 A
VGS = 4.5 V, ID = 9.4 A,TJ = 125°C
10
14
m
13 18
14 21
VGS = 4.5V, VDS = 5 V
19
A
VDS = 5 V, ID = 9.4 A
47
S
Dynamic Characteristics
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
VDS = 10 V, V GS = 0 V,
f = 1.0 MHz
1821
pF
440
pF
208
pF
Switching Characteristics
td(on)
Turn–On Delay Time
tr
Turn–On Rise Time
td(off)
Turn–Off Delay Time
tf
Turn–Off Fall Time
Qg
Total Gate Charge
Qgs
Gate–Source Charge
Qgd
Gate–Drain Charge
(Note 2)
VDD = 10 V, ID = 1 A,
VGS = 4.5 V, RGEN = 6
VDS = 10 V, ID = 9.4 A,
VGS = 4.5 V
10 20
ns
15 27
ns
34 55
ns
16 29
ns
16 23
nC
3
nC
4
nC
Drain–Source Diode Characteristics and Maximum Ratings
IS
Maximum Continuous Drain–Source Diode Forward Current
VSD
Drain–Source Diode Forward
Voltage
VGS = 0 V, IS = 1.3 A (Note 2)
1.3
A
0.7 1.2
V
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design.
a) 78°C/W when
mounted on a 0.5in2
pad of 2 oz copper
b) 125°C/W when
mounted on a 0.02
in2 pad of 2 oz
copper
c) 135°C/W when mounted on a
minimum mounting pad.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%
3. The diode connected between the gate and source serves only as protection against ESD. No gate overvoltage rating is implied
FDS6898AZ_F085 Rev. A
2
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