DM74ALS165(2007) View Datasheet(PDF) - Fairchild Semiconductor
Part Name
Description
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DM74ALS165 Datasheet PDF : 7 Pages
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DM74ALS165
8-Bit Parallel In/Serial Out Shift Register
May 2007
tm
Features
■ Complementary outputs
■ Direct overriding load (data) inputs
■ Gated clock inputs
■ Parallel-to-serial data conversion
General Description
The DM74ALS165 is an 8-bit serial register that, when
clocked, shifts the data toward serial output, QH. Parallel-
in access to each stage is provided by eight individual
direct data inputs that are enabled by a low level at the
SH/LD input. The DM74ALS165 also features a clock
inhibit function and a complemented serial output, QH.
Clocking is accomplished by a LOW-to-HIGH transition
of the CLK input while SH/LD is held HIGH and CLK INH
is held LOW. The functions of the CLK and CLK INH
(clock inhibit) inputs are interchangeable. Since a LOW
CLK input and a LOW-to-HIGH transition of CLK INH will
also accomplish clocking, CLK INH should be changed
to the high level only while the CLK input is HIGH. Paral-
lel loading is inhibited when SH/LD is held HIGH. The
parallel inputs to the register are enabled while SH/LD is
LOW independently of the levels of CLK, CLK INH, or
SER inputs.
Ordering Information
Order
Number
Package
Number
Package Description
DM74ALS165M
M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering number.
Connection Diagram
©1986 Fairchild Semiconductor Corporation
DM74ALS165 Rev. 1.2
www.fairchildsemi.com
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