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74AC373M_97 View Datasheet(PDF) - STMicroelectronics

Part Name74AC373M_97 ST-Microelectronics
STMicroelectronics ST-Microelectronics
DescriptionOCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING
74AC373M_97 Datasheet PDF : 10 Pages
1 2 3 4 5 6 7 8 9 10
74AC373
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
1
2, 5, 6,
9, 12, 15,
16, 19
3, 4, 7,
8, 13, 14,
17, 18
11
10
20
SYMBOL
OE
Q0 to Q7
NAME AND FUNCTION
3 State Output Enable
Input (Active LOW)
Data Inputs
D0 to D7 3 State Outputs
LE
GND
VCC
Latch Enable
Input
Ground (0V)
Positive Supply Voltage
TRUTH TABLE
IN PUT S
OE
LE
D
H
X
X
L
L
X
L
H
L
L
H
H
X: DON’T CARE
Z: HIGH IMPEDANCE
*: Q OUTPUTS ARE LATCHED AT THE TIME WHEN THE INPUT IS TAKEN LOW LOGIC LEVEL.
OUTPUTS
Q
Z
NO CHANGE
L
H
LOGIC DIAGRAMS
2/10
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DESCRIPTION
The AC373 is an advanced high-speed CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power applications mantaining high speed operation similar to equivalent Bipolar Schottky TTL.
These 8 bit D-Type latch are controlled by a latch enable input (LE) and an output enable input(OE).
While the LE inputs is held at a high level, the Q outputs will follow the data input precisely or inversely. When the LE is taken low, the Q outputs will be latched precisely or inversely at the logic level of D input data. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state.
This device is designed to interface directly High Speed CMOS systems with TTL and NMOS components.
All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

■ HIGH SPEED: tPD = 5 ns (TYP.) at VCC = 5V
■ LOW POWER DISSIPATION:
   ICC = 8 µA (MAX.) at TA = 25 °C
■ HIGH NOISE IMMUNITY:
   VNIH = VNIL = 28% VCC (MIN.)
■ 50Ω TRANSMISSION LINE DRIVING CAPABILITY
■ SYMMETRICAL OUTPUT IMPEDANCE:
   |IOH| = IOL =24 mA (MIN)
■ BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL
■ OPERATING VOLTAGE RANGE:
   VCC (OPR) = 2V to 6V
■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 373
■ IMPROVED LATCH-UP IMMUNITY

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