RS5C348B_95 View Datasheet(PDF) - RICOH Co.,Ltd.

Part Name

Description

View to exact match

RS5C348B_95

4-WIRE SERIAL INTERFACE REAL-TIME CLOCK ICS WITH VOLTAGE MONITORING FUNCTION

RICOH Co.,Ltd. 

R×5C348A/B

3. Oscillation Halt Sensing and Supply Voltage Monitoring

The oscillation halt sensing circuit is configured to record a halt in the oscillation of 32.768-kHz clock pulses. The

supply voltage monitoring circuit is configured to record a drop in supply voltage below a threshold voltage of 2.1 or

1.6 volts. For these functions, the real-time clock has two flag bits (ie. the XSTP bit for the former and the VDET bit

for the latter) in which 1 is set once and this setting is maintained until 0 is written.

When the XSTP bit is set to 1 for the oscillation halt sensing circuit, the VDET bit is reset to 0 for the supply voltage

monitoring circuit. The relationship between the XSTP and VDET bits is shown in the table below. The oscillation

halt sensing circuit operates only when the CE pin is Low. The sensing result is maintained after the CE pin

changes from “L” to “H”(see “6.4 Connection of CE Pin”).

XSTP

0

0

1

VDET

0

1

*

Conditions of supply voltage and oscillation

No drop in supply voltage below threshold voltage and no halt in oscillation

Drop in supply voltage below threshold voltage and no halt in oscillation

Halt on oscillation

Threshold voltage (2.1 or 1.6 volts)

Supply voltage

Oscillation by 32.768-kHz clock pulses

Normal voltage detector

Supply voltage monitoring (VDET)

Oscillation halt sensing (XSTP)

Internal initialization Setting XSTP and

period

VDET bits to 0

(1 to 2 seconds)

Setting VDET bit to 0

Setting XSTP and

VDET bits to 0

When the XSTP bit is set to 1 in the control register 2, the (0), F6 to F0, WALE, DALE, 12/24, CLEN2, TEST, CT2, CT1,

CT0, VDSL, VDET, SCRATCH1, SCRATCH 2, SCRATCH3, CLEN1, CTFG, WAFG, and DAFG bits are reset to 0 in the

oscillation adjustment register, the control register 1, and the control register 2. The XSTP bit is also set to 1 at power-

on from 0 volts. When the CE pin is “H” at power on from 0 volts, the XSTP bit is undefined, and the above bits are

undefined (see “6.4 Connection of CE Pin”). Note that the XSTP bit may be locked to 0 and the internal register

broken upon instantaneous power-down.

33

Share Link: