M34551E4-XXXFP View Datasheet(PDF) - Renesas Electronics

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M34551E4-XXXFP

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER

Renesas Electronics 

MITSUBISHI MICROCOMPUTERS

4551 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for

INFRARED REMOTE CONTROL TRANSMITTER

(2) Internal state at reset

Table 14 shows port state at reset, and Figure 31 shows

internal state at reset (they are retained after system is

released from reset).

Table 14 Port state at reset

Name

Function

D0–D4, D5/INT

D0–D4, D5

D6/XCIN, D7/XCOUT

P00–P03

P10–P13

D6, D7

P00–P03

P10–P13

P20/SEG16–P23/SEG19

SEG0–SEG15

COM0–COM3

P20–P23

SEG0–SEG15

COM0–COM3

CARR

CARR

Notes 1: Output latch is set to “1.”

2: The pull-up transistor is turned off.

The contents of timers, registers, flags and RAM except those

shown in Figure 31 are undefined, so set the initial values to

them.

State

High impedance (Note 1)

“H” (VDD) level (Note 1)

(Notes 1, 2)

High impedance

VLC3 (VDD) level

“L” (VSS) level

• Program counter (PC) .............................................................0......0......0......0......0......0. 0 0 0 0 0 0 0 0

Address 0 in page 0 is set to program counter.

• Interrupt enable flag (INTE) ..................................................................................0. (Interrupt disabled)

• Power down flag (P) ............................................................................................0..

• External 0 interrupt request flag (EXF0) ..............................................................0.

• Interrupt control register V1 ................................................................0......0......0......0. (Interrupt disabled)

• Interrupt control register I1 .................................................................0......0......0......0.

• Timer 1 interrupt request flag (T1F) .....................................................................0.

• Timer 2 interrupt request flag (T2F) .....................................................................0.

• Watchdog timer flag (WDF) ..................................................................................0.

• Watchdog timer enable flag (WEF) ......................................................................0.

• Timer control register W1 ...................................................................0......0......0......0. (Prescaler stopped)

• Timer control register W2 ...................................................................0......0......0......0. (Timer 1 stopped)

• Timer control register W3 ...............................................................................0......0. (Timer LC stopped)

• Clock control register MR ...................................................................1......0......0......0.

• Carrier wave selection register C1 .....................................................0......1......1......1.

• Carrier wave output control register C2 ..............................................................0..

• Carrier wave generating control flag CR ..............................................................0. (Carrier wave output disabled)

• LCD control register L1 .......................................................................0......0......0.....0.. (LCD off)

• LCD control register L2 .......................................................................1......1......1.....1.. (Port P2 selected)

• Pull-up control register PU0 ...............................................................0......0......0......0.

• General-purpose register V2 ..............................................................0......0......0......0.

• Carry flag (CY) ......................................................................................................0.

• Register A ..........................................................................................0......0......0......0..

• Register B ..........................................................................................0......0......0......0..

• Register D ................................................................................................!......!......!..

• Register E ..................................................................!......!......!......!......!......!......!......!..

• Data pointer X .....................................................................................0......0......0.....0..

• Data pointer Y .....................................................................................0......0......0.....0..

• Data pointer Z .................................................................................................!......!.

• Stack pointer (SP) ....................................................................................1......1......1..

“!” represents undefined.

Fig. 31 Internal state at reset

31

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