M34551E8 View Datasheet(PDF) - Renesas Electronics

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M34551E8

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER

Renesas Electronics 

MITSUBISHI MICROCOMPUTERS

4551 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for

INFRARED REMOTE CONTROL TRANSMITTER

(5) Stack registers (SKS) and stack pointer (SP)

Stack registers (SKs) are used to temporarily store the

contents of program counter (PC) just before branching until

returning to the original routine when;

• branching to an interrupt service routine (referred to as

an interrupt service routine),

• performing a subroutine call, or

• executing the table reference instruction (TABP p).

Stack registers (SKs) are eight identical registers, so that

subroutines can be nested up to 8 levels. However, one of

stack registers is used when using an interrupt service routine

or when executing a table reference instruction. Accordingly,

be careful not to stack over when performing these operations

together. The contents of registers SKs are destroyed when

8 levels are exceeded.

The register SK nesting level is pointed automatically by 3-

bit stack pointer (SP). The contents of the stack pointer (SP)

can be transferred to register A with the TASP instruction.

Figure 5 shows the stack registers (SKs) structure.

Figure 6 shows the example of operation at subroutine call.

(6) Interrupt stack register (SDP)

Interrupt stack register (SDP) is a 1-stage register. When an

interrupt occurs, this register (SDP) is used to temporarily

store the contents of data pointer, carry flag, skip flag, register

A, and register B just before an interrupt until returning to the

original routine.

Unlike the stack registers (SKs), this register (SDP) is not

used when executing the subroutine call instruction and the

table reference instruction.

(7) Skip flag

Skip flag controls skip decision for the conditional skip

instructions and continuous described skip instructions. When

an interrupt occurs, the contents of skip flag is stored

automatically in the interrupt stack register (SDP) and the

skip condition is retained.

Program counter (PC)

Executing the subroutine

call or table reference

instruction

Executing the return or

table reference instruction

SK0

(SP) = 0

SK1

(SP) = 1

SK2

(SP) = 2

SK3

(SP) = 3

SK4

(SP) = 4

SK5

(SP) = 5

SK6

(SP) = 6

SK7

(SP) = 7

Stack pointer (SP) points “7” at reset or

returning from RAM back-up mode. It points “0”

by executing the first BM instruction, and the

contents of program counter is stored in SK0.

When the BM instruction is executed after eight

stack registers are used ((SP) = 7), (SP) = 0

and the contents of SK0 is destroyed.

Fig. 5 Stack registers (SKs) structure

(SP)

(SK0)

(PC)

0

000116

SUB1

Main program

Subroutine

Address

000016 NOP

000116 BM SUB1

000216 NOP

SUB1 :

NOP

·

·

·

RT

(PC) (SK0)

(SP) 7

Note: Returning to the BM instruction execution

address with the RT instruction, and the BM

instruction is equivalent to the NOP instruction.

Fig. 6 Example of operation at subroutine call

9

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