CXP740056/740096/740010
AC Characteristics
(1) Clock timing
Item
Symbol Pin
(Ta = –20 to +75°C, VDD = 2.7 to 5.5V, Vss = 0V reference)
Conditions
Min. Typ. Max. Unit
System clock frequency fC
XTAL
VDD = 4.5 to 5.5V
Fig. 1, Fig. 2
1
EXTAL
1
24
MHz
12
System clock input pulse tXL,
width
tXH
Fig. 1, Fig. 2 VDD = 4.5 to 5.5V 28
EXTAL External clock drive
37.5
ns
System clock input
rise time, fall time
tCR,
tCF
EXTAL
Fig. 1, Fig. 2
External clock drive
200 ns
Event count input clock tEH,
pulse width
tEL
EC
Fig. 3
tsys + 50∗1
ns
Event count input clock tER,
rise time, fall time
tEF
EC
Fig. 3
20 ms
System clock frequency fC
TEX
TX
VDD = 2.7 to 5.5V
Fig. 2 (32kHz clock applied
condition)
32.768
kHz
Event count input clock tTL,
pulse width
tTH
TEX
Fig. 3
10
µs
Event count input clock tTR,
rise time, fall time
tTF
TEX
Fig. 3
20 ms
∗1 tsys indicates the three values below according to the upper two bits (CPU clock selection) of the clock
control register (CLC: 000FEh).
tsys [ns] = 2000/fc (upper two bits = “00”), 4000/fc (upper two bits = “01”), 16000/fc (upper two bits = “11”)
1/fc
EXTAL
tXH
tCF
tXL
Fig. 1. Clock timing
VDD – 0.4V (VDD = 4.5 to 5.5V)
VDD – 0.3V
0.4V (VDD = 4.5 to 5.5V)
0.3V
tCR
Crystal oscillation
Ceramic oscillation
External clock
32kHz clock applied condetions
crystal oscillation
EXTAL XTAL
C1
C2
EXTAL XTAL
74HC04
TEX
C1
TX
C2
Fig. 2. Clock applied conditions
TEX
EC0
EC1
EC2
0.8VDD
0.2VDD
tEH
tEF
tEL
tER
tTH
tTF
tTL
tTR
Fig. 3. Event count clock timing
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