Figure 3: 16 Meg x 16
Column Address
Counter
Row Decoder
Memory Array
Bank 0
256Mb: x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
Functional Block Diagrams
A0–A19, B0, B1, B2
Column Address
Buffer
Row Address
Buffer
Row Decoder
Memory Array
Bank 1
Row Decoder
Memory Array
Bank 2
Refresh
Counter
Row Decoder
Memory Array
Bank 3
Row Decoder
Memory Array
Bank 4
Row Decoder
Memory Array
Bank 5
Row Decoder
Memory Array
Bank 6
Row Decoder
Memory Array
Bank 7
Data Valid
Data Read Strobe
Input Buffers Output Buffers Control Logic and Timing Generator
DVLD
DQS[1:0], DQS#[1:0]
DQ0–DQ15
Notes: 1. When the BL = 4 setting is used, A19 is a “Don’t Care.”
2. In the 16 Meg x 16 configuration, only DQS[1:0] and DQS#[1:0] are used.
pdf: 09005aef81121545/source: 09005aef810c0ffc
256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN
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