MT49H16M16 View Datasheet(PDF) - Micron Technology
Part Name
Description
View to exact match
MT49H16M16 Datasheet PDF : 38 Pages
| |||
256Mb: x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
Recommended DC Operation Ranges
Table 20: DC Electrical Characteristics and Operating Conditions
0°C ≤ TC ≤ +95°C; +1.7V ≤ VDD ≤ +1.95V unless otherwise noted
Description
Conditions
Symbol
MIn
Max
Units Notes
Input high (Logic 1) voltage
Input low (Logic 0) voltage
Output high voltage
Output low voltage
Input high (Logic 1) voltage
Input low (Logic 0) voltage
Output high voltage
Output low voltage
Clock input leakage current
Input Leakage current
Output leakage current
Reference voltage current
Matched impedance mode
Matched impedance mode
Matched impedance mode
Matched impedance mode
HSTL strong
HSTL strong
HSTL strong
HSTL strong
0V ≤ VIN ≤ VDDQ
VIH
VREF + 0.15 VDDQ + 0.3
V
VIL
VSSQ - 0.3 VREF - 0.15
V
VOH
VDDQ
V
VOL
0
V
VIH
VREF + 0.1 VDDQ + 0.3
V
VIL
VSSQ - 0.3 VREF - 0.1
V
VOH VDDQ - 0.4
V
VOL
0.4
V
ILC
-5
5
µA
ILI
-5
5
µA
ILO
-5
5
µA
IREF
-5
5
µA
1, 2
1, 2
1, 3, 4
1, 3, 4
1, 2
1, 2
1, 3, 4
1, 3, 4
Notes: 1. All voltages referenced to VSS (GND).
2. Overshoot: VIH(AC) ≤ VDD + 0.7V for t ≤ tCK/2
Undershoot: VIL(AC) ≥ −0.5V for t ≤ tCK/2
During normal operation, VDDQ must not exceed VDD. Control input signals may not
have pulse widths less than tCK/2 or operate at frequencies exceeding tCK (MAX).
3. AC load current is higher than the shown DC values. AC I/O curves are available upon
request.
4. HSTL outputs meet JEDEC HSTL Class I and Class II standards.
Table 21: Capacitance
Description
Address/Control input capacitance
Input/Output capacitance (DQ)
Clock capacitance
Conditions
TA = 25°C; f = 1 MHz
Symbol
CI
CO
CCK
MIn
2.0
2.0
2.0
Max
4.0
4.0
4.0
Units
pF
pF
pF
Table 22: AC Electrical Characteristics and Operating Conditions
0°C ≤ TC ≤ +95°C; +1.7V ≤ VDD ≤ +1.95V unless otherwise noted
Description
Input high (Logic 1) voltage
Input low (Logic 0) voltage
Input high (Logic 1) voltage
Input low (Logic 0) voltage
Conditions
Matched impedance mode
Matched impedance mode
HSTL strong
HSTL strong
Symbol
VIH
VIL
VIH
VIL
MIn
VREF + 0.3
VSSQ - 0.3
VREF + 0.2
VSSQ - 0.3
Max
VDDQ + 0.3
VREF - 0.3
VDDQ + 0.3
VREF - 0.2
Units
V
V
V
V
Figure 31: Output Test Conditions
VDDQ/2
50 Ohm
DQ
Test point
10 pF
pdf: 09005aef81121545/source: 09005aef810c0ffc
256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN
36
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001 Micron Technology, Inc. All rights reserved.
|
|
Share Link: 